/* Verilog-only additions layered on top of digital-electronics.css's .de-lesson prose
   (tables, boxes, takeaways, figures are all reused as-is -- this file only adds what
   a code-heavy lesson needs that a definition-heavy one didn't: a code listing block and
   a terminal-style simulator-output block). */

.de-lesson pre.vl-code { margin: 18px 0; padding: 16px 18px; border-radius: 10px; background: var(--ps-soft); border: 1px solid var(--ps-line); overflow-x: auto; }
.de-lesson pre.vl-code code { padding: 0; background: none; font-size: 0.88rem; line-height: 1.6; color: var(--ps-ink); white-space: pre; }
.vl-code-label { display: block; margin: 18px 0 -6px; font-size: 0.78rem; font-weight: 700; letter-spacing: 0.04em; text-transform: uppercase; color: var(--ps-muted); }

/* Simulator/terminal output: a permanently-dark card regardless of page theme, same
   convention the site already uses for inline SVG diagrams (self-contained dark cards). */
.de-lesson pre.vl-sim { margin: 10px 0 18px; padding: 14px 18px; border-radius: 10px; background: #0f172a; overflow-x: auto; }
.de-lesson pre.vl-sim code { padding: 0; background: none; font-size: 0.85rem; line-height: 1.6; color: #cfdcd4; white-space: pre; }
.de-lesson pre.vl-sim .vl-pass { color: #5bd083; font-weight: 700; }
.de-lesson pre.vl-sim .vl-fail { color: #f87171; font-weight: 700; }

@media (max-width: 640px) {
  .de-lesson pre.vl-code, .de-lesson pre.vl-sim { padding: 12px 14px; font-size: 0.85em; }
}