# Genus and SDC command cheat sheet

Units: time in ns, capacitance in pF for SDC commands. Genus database queries return fF.

## Setup
| Task | Command |
|---|---|
| Library search path | `set_db init_lib_search_path {. /path/libs}` |
| RTL search path | `set_db init_hdl_search_path ./rtl` |
| Script search path | `set_db script_search_path ./scripts` |
| Load library | `set_db library typical.lib` |
| Discourage a cell | `set_db [get_db lib_cells *BUFX1] .avoid true` |
| Protect a module | `set_db [get_db modules *blk] .dont_touch true` |

## Load and build
| Task | Command |
|---|---|
| Read RTL | `read_hdl -language v2001 file.v` |
| Read SystemVerilog | `read_hdl -language sv file.sv` |
| Define a macro | `read_hdl -define WIDTH=16 file.v` (quote as `-define "WIDTH = 16"` if your version needs it) |
| Read a netlist | `read_hdl -netlist net.v` |
| Elaborate | `elaborate top` |
| Override parameters | `elaborate top -parameters {{W 16}}` |
| Message summary | `report_messages` |

## Constraints (SDC)
| Task | Command |
|---|---|
| Read constraints | `read_sdc file.sdc` |
| Clock | `create_clock -name clk -period 2.0 [get_ports clk]` |
| Duty cycle | `create_clock -name c -period 10 -waveform {0 3} [get_ports c]` |
| Uncertainty | `set_clock_uncertainty 0.1 [get_clocks clk]` |
| Latency | `set_clock_latency 0.8 [get_clocks clk]` |
| Input delay | `set_input_delay 0.4 -clock clk [get_ports din]` |
| Output delay | `set_output_delay 0.5 -clock clk [get_ports sum]` |
| Driver model | `set_driving_cell -lib_cell BUFX2 [get_ports din]` |
| Output load | `set_load 0.02 [all_outputs]` |
| False path | `set_false_path -from [get_ports rst_n]` |
| Multicycle (pair) | `set_multicycle_path 2 -setup ...` then `set_multicycle_path 1 -hold ...` |
| Max delay | `set_max_delay 0.9 -from ... -to ...` |
| Clock groups (unrelated clocks) | `set_clock_groups -asynchronous -group {a} -group {b}` |
| Clock groups (never active together) | `set_clock_groups -physically_exclusive -group {a} -group {b}` |
| Max transition | `set_max_transition 0.3 [current_design]` |
| Max fanout | `set_max_fanout 16 [current_design]` |
| Max capacitance | `set_max_capacitance 0.1 [all_outputs]` |

## Synthesis
| Task | Command |
|---|---|
| Generic stage | `syn_generic` |
| Map to library | `syn_map` |
| Incremental optimization | `syn_opt` |
| Effort (each stage) | `set_db syn_generic_effort medium` (also `syn_map_effort`, `syn_opt_effort`) |
| Effort (all stages) | `set_db syn_global_effort medium` |
| CPUs | `set_db max_cpus_per_server 8` |
| Promote a submodule | `create_derived_design -name blk inst` |
| Save derived constraints | `write_script blk > blk.con` |
| Remove an object | `delete_obj blk` |

## Power, retiming, hierarchy
| Task | Command |
|---|---|
| Enable clock gating | `set_db lp_insert_clock_gating true` |
| Group size limits | `set_db design:* .lp_clock_gating_min_flops 6` / `.lp_clock_gating_max_flops 18` |
| Clock-gating report | `report_clock_gating` |
| Retime a module | `set_db module:top/blk .retime true` |
| Keep hierarchy | `set_db auto_ungroup none` |

## Reports
| Task | Command |
|---|---|
| Worst path | `report_timing` |
| Constraint lint | `report_timing -lint` |
| Between points | `report_timing -from X -to Y` |
| One exception | `report_timing -exceptions name` |
| One cost group | `report_timing -group name` |
| Area by module | `report_area` |
| Cell usage | `report_gates` |
| Save a report | `report_timing > timing.rpt` (`>>` appends) |

## Write out
| Task | Command |
|---|---|
| Netlist | `write_hdl > net.v` |
| One design | `write_hdl /designs/top/ > top.v` |
| Generic netlist | `write_hdl -generic > gen.v` |
| Constraints | `write_sdc > out.sdc` |
| Delays | `write_sdf > out.sdf` |
| Database | `write_db -to_file run.db` |
| Session script | `write_script > session.tcl` |

## Slack in one line
slack = required time - arrival time. WNS is the worst path. TNS is the sum of all negative slacks.