Routing and post-route
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Innovus PNR Mentor Guide

Routing, Post-Route Optimization, Checks and Handoff: from estimates to routed wires

By the end of this chapter you will be able to route the checkpoint saved after clock tree synthesis, and check it. You will extract real parasitics, optimize against them, read the evidence with its limits, and hand a named candidate to finishing.

Why this chapter matters in a real project

Until now, the data wires in every timing report were estimates. Routing draws the real ones: metal shapes on specific layers, joined by vias, on tracks, around obstacles. Those shapes have length, resistance, capacitance and neighbors that the estimate never saw. So the slacks move.

In our example, one setup path loses 0.125 ns between estimate and route. A hold path that looked safe turns negative. Routing also creates new things to check: spacing, shorts, opens and antenna violations.

The cost of getting this stage wrong is high in both directions. If you read stale or partial reports, you hand off a design with real violations that finishing then has to unpick. If you chase every number without a diagnosis, you waste runs. Worse, you break one check while fixing another.

Prerequisites

The worked example is the invented design stream_acc. It has a 1000 x 1000 um core, two RAM macros u_buf_a and u_buf_b, and one ROM macro u_coef. The main clock clk_core has a 2.5 ns period. Time is in ns, distances in um and capacitance in pF.

Honesty note

Learning objectives

  1. Describe what routing changes in a database, what it leaves alone, and which evidence shows each change.
  2. Tell a route guide from detailed wiring, and a global-route result from a routable design.
  3. Set layers, rules, clock-net protection, and timing-driven and crosstalk-driven routing with native commands, then read the settings back.
  4. Read a congestion count as demand against capacity, find its cause, and change the cause rather than the symptom.
  5. Inspect a detailed route for completion, design-rule violations, antenna violations, clock-route integrity, detours and vias.
  6. Explain why routed wires change setup and hold slack, and measure the change against a baseline.
  7. Apply setup, hold and electrical repairs in an order that protects each from the others, and state what each repair costs.
  8. Read the timing, electrical, violation and connectivity reports, say what each one does not prove, and recognize a stale report.
  9. Debug from a symptom to a confirmed cause, then classify the candidate as clean, accepted with documented exceptions, or not ready.

The whole stage fits on one page, in Figure 1. Come back to it whenever you lose your place.

Routing and post-route on one page
Two phases: route and inspect, then measure, repair and decide
Routing and post-route on one page
Figure 1 The stage on one page: Phase A builds and checks the wires, Phase B measures and repairs timing, and the decision closes it. Numbers are the chapter's illustrative example.

What to notice: Phase A ends with a saved checkpoint, and every Phase B candidate is measured against the R0 baseline.

1  Where routing fits

Until now, the data wires in the timing report were estimates. The clock wires were whatever clock tree synthesis had routed. Routing now draws the real signal wires. That changes three things: timing, the set of checks, and how hard the database is to change.

1.1  The handoff from the previous stage

The post-CTS stage ended with a saved checkpoint and a handoff note. The note says:

This chapter uses that note as input, but not blindly. You restore the checkpoint and check what came back, as "Confirm the starting checkpoint" shows.

The flow in Figure 2 runs from that checkpoint to finishing.

The two phases of this chapter
Phase A routes and inspects; Phase B extracts, optimizes, reports and decides
The two phases of this chapter
Figure 2 Phase A builds the wires and ends with a saved routed checkpoint. Phase B measures, repairs, reports and decides. A dashed arrow returns to a saved candidate when an idea fails.

What to notice: The routed checkpoint is saved at the end of Phase A, so every Phase B experiment can start from it.

1.2  What routing adds

Routing adds signal wires and vias. For clock nets, it adds the clock wires that were reserved earlier. By itself, routing does not move cells, change the clock tree or alter the power grid. Repairs such as antenna diodes can add cells, though.

A router can fail a net in three different ways:

Each of those has a different consequence, and the evidence for each is different.

1.3  Why routed parasitics change timing

An estimate models a wire from the placement and an early route. It is not detailed geometry. A routed wire has a real length, real layers, vias, pin access and real neighbors. Three effects follow:

These effects are not small. In our example, one path loses 0.125 ns between estimate and route. A hold path that looked safe turns negative (see "Extract and assess").

1.4  Two phases

This chapter separates two jobs, because they answer different questions.

Finishing comes after both phases: fillers, decoupling cells, metal fill and signoff checks. Finishing can reopen timing. Thus this handoff is a stage decision, not a signoff.

Takeaway Phase A answers "is it wired and legal?". Phase B answers "does it time, and can it go forward?". Keep the two questions apart.

Phase A: Routing

Phase A begins

Phase A takes the accepted post-CTS checkpoint and confirms it. It configures the router, builds the guides, draws the detailed wires and inspects the result. It ends with a saved routed checkpoint.

2  Confirm the starting checkpoint

Routing makes the physical database much harder to change. Some defects are cheap to fix before routing: an illegal cell, a missing clock rule, a broken power connection. After routing, each becomes an ECO (engineering change order). Spend ten minutes here to avoid a day later.

2.1  Restore, replay and read back

Restore the checkpoint and look at what came back. Do not rely on your memory of what was saved.

Start a new Innovus session for every restore. The tool does not support loading another database while a design is already in memory. This chapter does not use an unload command. So when a later step says "restore", close the session and start a fresh one.

START - RESTORE THE ACCEPTED POST-CTS CHECKPOINT (FRESH SESSION)
innovus> restoreDesign handoff_cts.enc.dat stream_acc ;# load the post-CTS checkpoint

The checkpoint and design names are examples to adapt. Database identity is not analysis identity, though. Replay the approved site setup, read the configuration back, and compare the active analysis views with the views the project requires.

CHECK - REPLAY THE SITE SETUP AND READ THE CONFIGURATION BACK (ANALYSIS ONLY)
innovus> source site_setup.tcl ;# replay the approved site setup
innovus> getAnalysisMode ;# print the analysis mode
innovus> getExtractRCMode ;# print the extraction mode
innovus> getDelayCalMode -SIAware ;# is delay calculation crosstalk-aware?
innovus> all_analysis_views -type setup ;# list the active setup views
innovus> all_analysis_views -type hold ;# list the active hold views
innovus> check_timing -verbose > start_check_timing.rpt ;# look for missing constraints

Here is what each piece does:

Then run the readiness checks.

CHECK - READINESS BEFORE ROUTING (ANALYSIS ONLY)
innovus> checkPlace ;# are all cells still legally placed?
innovus> check_design -type route ;# the routing readiness check
innovus> report_clocks -generated ;# list clocks, including generated clocks
innovus> timeDesign -postCTS -outDir timing_start -prefix start ;# starting setup
innovus> timeDesign -postCTS -hold -outDir timing_start -prefix start ;# starting hold

2.2  What blocks routing, and what proceeds with tracking

Not every finding stops the flow. Table 1 separates the findings that block routing from the ones you track and carry forward.

Table 1 Findings before routing: block, or proceed with tracking
FindingDecisionWhy
checkPlace reports illegal or overlapping cellsBlocksRouting around an illegal cell wastes the route, and the cell moves later
check_design -⁠type route reports errorsBlocksThe tool is saying that the design is not ready to route
Clock trees missing, or clocks not propagatedBlocksTiming-driven routing then optimizes against the wrong clock
Clock routing rules not recorded in the handoffBlocksYou cannot protect what you cannot name
A required analysis view is not active, or check_timing shows a missing constraint with no reasonBlocksGood slack in the wrong view set proves nothing
Power connections incompleteBlocksSignal routing assumes the grid is there
Small setup or hold violations on estimated wiresProceeds, trackedReal wires replace the estimates in "Extract and assess", and the numbers will move
Antenna status unknownProceeds, trackedIt is a routing result, first visible after detailed route
A post-CTS waiver that is current, approved and still applicableProceeds, trackedCarry it into the acceptance record with its approval reference
What the evidence proves, and what it does not

Proves: on estimated wires, the starting design has setup WNS (worst negative slack) +0.040 ns. Hold WNS is +0.050 ns in the intended views. Does not prove: that either number survives routing. They are the baseline for "Extract and assess", nothing more.

3  Routing essentials

Every routing decision in this chapter rests on six ideas: tracks, layers, vias, guides, capacity and rules. Learn them once on small drawings. The congestion and violation cases later then read as simple counts.

3.1  Tracks and layers

A routing layer has a preferred direction. For example, odd layers might run horizontally and even layers vertically, or the reverse, depending on the technology. Wires normally sit on tracks: evenly spaced lines in that direction, one wire wide.

Most regular routing follows the preferred tracks. Off-track geometry can exist. However, it must still satisfy the manufacturing grid, the technology rules and the routing policy. A wire in the wrong direction is legal in some technologies, but it uses resources fast, so the router avoids it.

Low layers are thin and narrow, so they are resistive and good for short local wires. High layers are wide and thick, so they are fast and good for long wires. That is a tendency, not a law. It is why timing repair often promotes long nets upward, and the benefit depends on the technology.

3.2  Vias

A via joins two adjacent layers. It is a cut with metal enclosure on both layers. Its footprint takes routing space through both the enclosure and the cut spacing. A via also has resistance of its own.

Route topology balances wire RC, via RC, pin access, design rules and reliability. So a layer change is sometimes the better choice and sometimes the cost.

Figure 3 shows a net that changes layer twice, and a second net that only crosses it.

A layer change, from above and from the side
Net X climbs M3 to M4 to M5; net Y crosses on M4 with no via
A layer change, from above and from the side
Figure 3 Net X starts on M3, goes up through a via to M4, and up again to M5. Net Y runs on M4 and crosses X where X is on M5, with no via. Not to scale.

What to notice: A crossing is not a connection. Only a cut with enclosure on both layers joins two layers.

3.3  Guides, then wires

Routing happens in two steps.

  1. Global route divides the die into rectangular gcells (global routing cells). It decides, net by net, which gcells each net will pass through. That decision is a guide.
  2. Detailed route then draws the real wires and vias on tracks, inside or near the guide, and fixes the design rules.

A guide does not give legal tracks or physical wire and via geometry. Global routing can still account for layers, as the 3D congestion report shows.

Figure 4 is a simplified 2D projection of the same net at both stages.

A guide and its detailed route
Same net, same coordinates, two stages
A guide and its detailed route
Figure 4 Left: five gcells form an L-shaped guide below a blockage, because B sits one row higher than A. Right: the detailed route uses three wires and four vias on tracks. Not to scale.

What to notice: The guide is not metal. The same five gcells become three wires and four vias.

Where the analogy breaks - read this twice

A guide is like a travel plan that lists the towns you will pass through. Detailed route is the drive itself, lane by lane.

  • A plan can look fine and still fail on the road. Zero overflow in global route does not promise a violation-free detailed route.
  • Unlike towns, gcells have a hard count of lanes (tracks). The plan is judged by counting them.

3.4  Capacity and demand

Each gcell edge has a capacity: the number of tracks that can cross it on the usable layers. It also has a demand: the number of wires that want to cross it. If demand exceeds capacity, the excess is overflow:

EXAMPLE - THE OVERFLOW FORMULA
overflow = max(0, demand - capacity)

With several layers, add up the positive overflows. Spare tracks on another layer do not cancel a blocked layer. Overflow means some wire must detour, change layer, or become a violation.

Figure 5 shows the arithmetic on one gcell edge.

Demand and capacity on one gcell edge
Eight wires want to cross; a second layer adds two tracks
Demand and capacity on one gcell edge
Figure 5 Left: eight wires want to cross six tracks, so two have no track. Right: two wires take a second layer that adds two tracks. Counts are invented.

What to notice: The arithmetic is the whole mechanism: 8 - 6 = 2, then 8 - 8 = 0.

3.5  Rules and blockages

The router obeys design rules from the technology: minimum width, minimum spacing, minimum area and via enclosure. Non-default rules (NDRs) give selected nets wider wires or more spacing, such as the clock rule from clock tree synthesis.

Blockages remove tracks from a region. A blockage helps when it protects something. It hurts when it is stale and nobody remembers why it was placed.

Takeaway A guide is a plan; detailed wires are the result. Capacity counts tracks, demand counts wires, and overflow is the excess, never negative. A via costs footprint and resistance. A blockage nobody can explain deserves a question before it deserves respect.

4  Prepare the routing configuration

Left alone, the router uses defaults. Those defaults do not know your clock rules, your timing priorities or your antenna fix. Each setting below answers one question. Set it before routing, read it back, and write down what you changed. A setting you did not read back is only a setting you intended.

4.1  Which layers may signal nets use?

Two different commands do two different jobs. Global bounds belong to setDesignMode. It takes the lowest and highest routing layer by technology layer name.

CONFIGURE - GLOBAL ROUTING LAYER BOUNDS (SETTINGS ONLY)
innovus> setDesignMode -bottomRoutingLayer M2 -topRoutingLayer M7 ;# signals on M2-M7

The layer names are examples. In this invented design the approved top layer is M7. The residual M7 tracks are approved for signals after the power-ground reservations. The congestion case in the next section depends on that. A blockage removal cannot make a layer usable above a hard top bound. So the bound and the capacity table have to agree.

Per-net preference belongs to setAttribute, with layer numbers from your technology. A preference is not a bound and not a guarantee. The router can leave the preferred layers when it must. setNanoRouteMode has no global layer-bound option, so do not look for one there.

CONFIGURE - PREFERRED LAYERS FOR ONE CLOCK NET (SETTINGS ONLY)
innovus> setAttribute -net clk_core_trunk1 -bottom_preferred_routing_layer 5 \
    -top_preferred_routing_layer 6 -preferred_routing_layer_effort high ;# layers 5-6

4.2  How do the clock nets stay as they were built?

Clock tree synthesis reserved clock routing rules and layers. The router must honor them. It should also leave clock nets that are already routed alone unless it must change them.

CONFIGURE - CLOCK-NET BEHAVIOR (SETTINGS ONLY)
innovus> setNanoRouteMode -route_strict_honor_route_rule true ;# harden NDR spacing
innovus> setNanoRouteMode -route_route_clock_nets_first true ;# clock nets first
innovus> setNanoRouteMode -route_fix_clock_nets true ;# keep clock net status

This chapter's main flow runs globalRoute and detailRoute separately. The two routeDesign options above control the alternative flow. Setting them is context, not proof that the clock was preserved in the split flow. Validate the clock with the physical clock reports after detailed route and on the final candidate.

Clock wires that do not move during routing can still move later. Post-route optimization can repair clock design-rule violations through ccopt_pro. That is a clock-tree optimization step it can call. "The clock did not move" is a measurement, not an assumption.

4.3  Should routing watch timing and crosstalk?

CONFIGURE - TIMING-DRIVEN AND CROSSTALK-DRIVEN ROUTING (SETTINGS ONLY)
innovus> setNanoRouteMode -route_with_timing_driven true ;# slack as a priority
innovus> setNanoRouteMode -route_with_si_driven true ;# reduce crosstalk

4.4  How should antenna violations be fixed?

An antenna violation is charge collected on a long wire during manufacturing that can damage a connected gate. By default the router fixes it by layer hopping. It moves the long run up a layer, so less metal is attached at each manufacturing step. It can also insert a diode near the gate.

CONFIGURE - ANTENNA FIX (SETTINGS ONLY)
innovus> setNanoRouteMode -route_detail_fix_antenna true ;# repair antennas
innovus> setNanoRouteMode -route_antenna_diode_insertion true ;# allow diode insertion
innovus> setNanoRouteMode -route_antenna_cell_name ANTENNA_X1 ;# example diode cell name

4.5  How many vias, and how many cuts?

CONFIGURE - VIA CUT EFFORT (SETTINGS ONLY; CHECK THE VALUES FOR YOUR RELEASE)
innovus> setNanoRouteMode -route_detail_use_multi_cut_via_effort medium ;# more cuts

The values are low (the default), medium and high. Higher effort means more double cuts. Double cuts help yield and resistance, but they cost runtime and congestion.

4.6  Blockages

createRouteBlk places a routing blockage, and deleteRouteBlk removes one by name and layer. Both belong to the partition-floorplanning command set. No command in this flow prints all existing route blockages.

To find out which blockages exist, read the floorplan record or open the layout view. A blockage that you did not create and cannot explain is a finding for global route.

4.7  Read the settings back

Each setter has its own getter. One getter does not report another interface's state, and none of them reports actual geometry.

CHECK - PRINT THE SETTINGS INTO THE LOG (ANALYSIS ONLY)
innovus> getDesignMode -bottomRoutingLayer ;# read the lowest routing layer
innovus> getDesignMode -topRoutingLayer ;# read the highest routing layer
innovus> getAttribute -net clk_core_trunk1 ;# read the per-net attributes
innovus> getNanoRouteMode ;# read the router modes

getDesignMode reads the global layer bounds, getAttribute the per-net attributes, and getNanoRouteMode the router modes. Keep the output with the candidate. When two candidates differ, the first question is whether their settings were the same.

Common beginner mistake

Setting -⁠route_with_timing_driven true and assuming the timing problem is handled. The router uses the slacks it has, which are post-CTS slacks on estimated wires. It improves the odds. It does not replace the extract, repair and remeasure loop of Phase B.

5  Global route and congestion

Global route is cheap and fast. It shows where the design will struggle before any metal is drawn. Congestion that you find here costs one rerun. The same congestion found as hundreds of violations after detailed route costs a day.

5.1  Run global route and read the congestion

Table 2 summarizes what the main command does.

Table 2 Command card - globalRoute
FieldValue
RoleConstruct (guides)
Starts fromThe restored checkpoint, with the routing configuration in the session
ChangesNet-to-gcell assignments. No detailed wire yet
Ends atA guide for every signal net, and congestion counts per gcell
RUN - GLOBAL ROUTE, THEN READ THE CONGESTION (CHANGES THE DATABASE)
innovus> globalRoute ;# build a guide for every signal net
innovus> reportCongestion -overflow ;# report gcell overflow
innovus> reportCongestion -hotSpot -3d ;# report hotspots, layer by layer

dumpNanoCongestArea is intended for use after routeDesign. This chapter does not rely on it for a global-route-only state. If you try it there in your release, treat the result as unverified. A line of its output has this form:

ILLUSTRATIVE OUTPUT - DUMPNANOCONGESTAREA LINE (INVENTED VALUES; LAYOUT DIFFERS)
gcell (412 380)        V: 0/6/20         H: -3/0/23

Read each group as a direction (V or H) with overflow / remaining / total tracks. The remaining and total values are added up over the layers of that direction.

The "capacity 23, demand 26" used below is hypothetical bookkeeping from the layer table in the congestion case. Keep it separate from anything a tool prints.

What the evidence proves, and what it does not

Proves: where the global router could not find capacity for every wire it wanted to place. Does not prove: that a design with no overflow will route without violations. Global route sees gcells, not tracks, spacing or vias. Detailed route decides those.

5.2  A congestion case: the channel between the two RAMs

In stream_acc, the horizontal count above sits in the narrow channel between u_buf_a and u_buf_b. Every wire that crosses from the left half of the design to the right passes there. Let us follow it from symptom to intervention.

Evidence. Overflow of 3 on the horizontal tracks of the channel. Total capacity 23, demand 26.

Competing causes. Either too many nets want to cross, or capacity is lower than it should be. These need different repairs: placement changes for the first, routing resources for the second. To tell them apart, count the capacity by layer (Table 3).

Table 3 Channel capacity by layer (invented counts)
LayerTracks in the channelTaken byUsable
M314nothing14
M514the clock bundle, which reserves 5 slots (an invented figure, not derived from 2x width and 2x space)9
M7146 power stripes, and a blockage over the other 80
Total23

The M7 row is the finding. The blockage covers 8 tracks that nobody uses for power. Its name suggests an old floorplan keep-out. Nobody on the team can say why it is still there.

Intervention. Confirm with the power owner that the blockage protects nothing, then delete it. Do not delete a blockage because it looks stale. Ask first.

REPAIR - REMOVE ONE CONFIRMED STALE BLOCKAGE
innovus> deleteRouteBlk -name blk_m7_chan -layer 7 ;# remove the stale M7 blockage

The blockage name and layer are examples. Resulting evidence. Capacity becomes 14 + 9 + 8 = 31. Demand is still 26, so overflow is 0 and the utilization is 26 / 31 = 84%. Rerun globalRoute and reportCongestion -⁠overflow to confirm that the gcell no longer appears.

Figure 6 draws the channel before and after the fix.

The channel between the two RAMs
Each square is one track slot across a cut line in the channel; demand is 26 wires
The channel between the two RAMs
Figure 6 Left: a stale M7 blockage leaves 23 usable slots for 26 wires. Right: with the blockage removed, M7 adds 8 slots. Counts are invented, not to scale.

What to notice: Removing one blockage adds 8 slots and ends the overflow: 26 / 31 = 84% used.

Common beginner mistake

Treating overflow as a router-effort problem, and raising effort settings when the cause is a blockage. Count capacity by layer first. If capacity is correct and demand is the problem, the repair is in placement or in the netlist. It belongs before routing, not after.

Stop and investigate

For this teaching flow, resolve significant or persistent overflow before detailed route. Small residual hotspots need project judgment and detailed-route evidence. They raise the risk of violations, but they do not prove that the design cannot be repaired.

6  Detailed route and inspect

Detailed route draws the real wires. It is the step that can fail in ways that global route could not predict. After it, you must answer five questions:

  1. Is every net connected?
  2. Are the design rules met?
  3. Is the antenna clean?
  4. Are the clock routes intact?
  5. Did anything take an unexpected path?

6.1  Run detailed route

Table 4 Command card - detailRoute
FieldValue
RoleConstruct
Starts fromThe guides from global route, with no significant overflow, and the routing configuration
ChangesWires and vias on tracks, plus optimization and antenna repair in the final passes
Ends atA routed database, still holding whatever violations the router could not remove
RUN - DETAILED ROUTE, THEN SAVE THE ROUTED STATE (CHANGES THE DATABASE)
innovus> detailRoute ;# draw wires and vias on tracks
innovus> saveDesign routed_raw.enc ;# save before any repair

Save before you repair. If the repair makes things worse, you can come back here.

Alternative flow - not part of the main run

routeDesign is the supercommand that runs global route and detailed route in one call. Its optional passes are not interchangeable:

  • -⁠trackOpt optimizes after track assignment and may involve model generation.
  • -⁠viaOpt optimizes vias after route and can involve search and repair.
  • -⁠wireOpt widens or shrinks wires under the modes you configured. It is not an unconditional timing gain.
  • -⁠viaPillarOpt inserts or upgrades via pillars where the technology and modes allow it.
  • -⁠clockEco is a clock-ECO routing context, not another ordinary signal pass.

Do not combine them blindly. With the timing-driven and crosstalk-driven options on, routeDesign runs the combined mode. Run check_design -⁠type route before it.

This chapter runs globalRoute and detailRoute separately for one reason. You can read congestion between them, and fix a blockage for the price of one global route. If you already trust the congestion picture, routeDesign is shorter.

6.2  Inspect the routed result

Run the checks in this order. Each answers one question, and a later check is hard to read if an earlier one fails.

CONFIGURE - THE PERSISTENT DESIGN-RULE CHECK MODE (SETTINGS ONLY)
innovus> set_verify_drc_mode -limit 1000 ;# stop listing after 1000 violations
CHECK - CONNECTIVITY, DESIGN RULES, ANTENNA (ANALYSIS ONLY)
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# opens, unrouted, loops
innovus> verify_drc -report A_drc_first.rpt ;# design rules on routed geometry
innovus> verify_antenna -report A_antenna_first.rpt ;# antenna ratios on routed nets

These habits keep the reports honest.

Is every net connected?

verifyConnectivity finds opens, unconnected wires, unconnected pins, loops, and partial or unrouted nets. It makes markers and a report. Shorts between nets appear as design-rule markers in the next check.

ILLUSTRATIVE OUTPUT - VERIFYCONNECTIVITY SUMMARY (INVENTED VALUES)
Begin Summary
  Open      : 0
  Unrouted : 0
  Loop      : 0
End Summary

Decision. Any open or unrouted net blocks the handoff. Does not prove: that the wires are legal, only that each net joins its pins.

Are the design rules met?

verify_drc checks the routed geometry against the technology rules. It leaves markers for the violation browser.

ILLUSTRATIVE OUTPUT - VERIFY_DRC FIRST PASS (INVENTED VALUES)
Violation Type         Count
Short                      3
Metal Spacing              6
Min Area                   2
Total                     11

The first pass in this example shows 11 violations. Your count will differ. What matters is whether the violations are local or clustered. Figure 7 shows three of the findings you meet most often.

Spacing, short and open
Three findings on the same kind of M3 wires
Spacing, short and open
Figure 7 A spacing violation is two nets too close. A short is two nets touching. An open is one net with a missing piece of wire. Not to scale.

What to notice: In a short, both nets are wrong. Each finding has its own repair.

Repair design-rule violations with ecoRoute -⁠fix_drc. It fixes the existing markers only. It reports an error if open nets exist, so settle connectivity first. Also make sure the markers are current: the verify_drc above just made them. Clear nothing by hand, run the check again, and compare the counts.

REPAIR - FIX THE EXISTING MARKERS, THEN CHECK AGAIN
innovus> ecoRoute -fix_drc ;# repair the current DRC markers
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# recheck connectivity
innovus> verify_drc -report A_drc_second.rpt ;# recheck design rules, new report name

In the example, the count goes from 11 to 0. Any physical repair can disturb the other checks. So connectivity, DRC (design rule check) and antenna checks all rerun after the last repair. Do not rerun only the check that prompted it.

If the count does not reach 0, go to "Debug common failures". Do not run ecoRoute -⁠fix_drc repeatedly and hope. A violation that survives two passes has a cause, and the cause is rarely in the router's effort.

Is the antenna clean?

verify_antenna checks antenna ratios on the routed nets. It needs antenna information in the LEF. Repair needs a real diode cell, its site and free space. The default report lists only violating layers.

ILLUSTRATIVE OUTPUT - VERIFY_ANTENNA (INVENTED VALUES)
Net n_7781   layer M3   ratio 512.0   limit 400.0   VIOLATION
Net n_9020   layer M4   ratio 431.0   limit 400.0   VIOLATION
Total antenna violations: 2

The limit is a property of the technology, not a number to adopt. The mechanism is simple. A long wire built on a low layer collects charge before the layer above it exists. The fix attaches less metal at that step (layer hopping) or gives the charge a path (a diode).

Figure 8 compares the two antenna fixes side by side.

An antenna violation and its two fixes
Before, layer hop and diode, on the same driver and gate
An antenna violation and its two fixes
Figure 8 Left: a long M3 wire on a gate, ratio 512 against a limit of 400. Middle: the long run moves to M5. Right: a diode on the net changes the applicable antenna criterion. Limit invented, not to scale.

What to notice: Layer hopping costs vias and a little congestion. A diode costs one cell and a pin on the net.

If the antenna settings were on and violations remain, route only those nets again. Clear the selection first and last, so that nothing else rides along.

REPAIR - ROUTE ONLY THE SELECTED NETS AGAIN
innovus> deselectAll ;# start with an empty selection
innovus> selectNet {n_7781 n_9020} ;# select the two antenna nets
innovus> detailRoute -select ;# reroute only the selected nets
innovus> deselectAll ;# clear the selection again
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# recheck connectivity
innovus> verify_drc -report A_drc_third.rpt ;# recheck design rules
innovus> verify_antenna -report A_antenna_second.rpt ;# recheck antenna

The net names are the example's. In the example both violations clear, 2 to 0, and the rerun connectivity and DRC stay clean. If they did not, the reroute would have traded one problem for another.

Are the clock routes intact?

A clock net routed with the wrong rule or on the wrong layer passes verifyConnectivity. It can still fail timing and electrical checks later. So read back what was drawn.

CHECK - CLOCK WIRES AND VIAS (ANALYSIS ONLY; EXAMPLE NET NAMES)
innovus> report_net_wires -net clk_core_trunk1 -file wires_trunk1.rpt ;# trunk 1
innovus> report_net_wires -net clk_core_trunk2 -file wires_trunk2.rpt ;# trunk 2
innovus> report_via -on_clock_nets -detail ;# via details on clock nets

Did anything take the long way around?

Detours, and layers you did not expect, show up as timing later. You can look for them now. report_route prints routing statistics, including via tables. -⁠multi_cut adds the share of multi-cut vias.

CHECK - ROUTE STATISTICS (ANALYSIS ONLY)
innovus> report_route -multi_cut ;# routing statistics with multi-cut via share

For a specific net, open the layout view of the path studied in "Extract and assess". Note a route much longer than the straight pin-to-pin distance, or one that jumps through many layers. Such a route is a finding, not necessarily a fault. A detour around a macro is correct if the straight way is blocked.

6.3  Checkpoint summary for Phase A

Table 5 collects the Phase A evidence in one place.

Table 5 Phase A evidence for the example
QuestionEvidenceExample result
Every net connected?verifyConnectivity0 opens, 0 unrouted
Design rules met?verify_drc11 first pass, 0 after ecoRoute -⁠fix_drc
Antenna clean?verify_antenna2 first pass, 0 after a reroute of those nets
Clock routes intact?report_net_wires, report_viaRule and layers as specified
Anything unexpected?report_route, layout viewOne macro detour, noted for "Extract and assess"

Save the design only after the last physical change has been followed by connectivity, DRC and antenna runs.

SAVE - THE ROUTED CHECKPOINT
innovus> saveDesign routed.enc ;# save the inspected routed checkpoint

End of Phase A - routed checkpoint saved The design now has routed, inspected signal wires. Connectivity and design-rule checks are clean, and routed.enc is saved. Phase B measures what those real wires did to timing. It does not route again unless a repair requires it.

Phase B: Post-route optimization

Phase B begins

Phase B extracts the real parasitics from the routed checkpoint. It measures timing and electrical limits against them, repairs in a protected order, and decides whether the result can go forward. It starts by measuring, not by repairing.

7  Extract and assess

You cannot repair what you have not measured. You cannot call a repair good without a baseline either. Extraction turns the drawn wires into resistance and capacitance. Timing analysis on those numbers is the first honest timing result of the flow. Save it as candidate R0 before you change anything.

Table 6 Command card - timeDesign -postRoute
FieldValue
Main commandtimeDesign -⁠postRoute -⁠expandedViews -⁠numPaths 200 -⁠outDir timing_route -⁠prefix R0, then the same with -⁠hold
RoleReport
Starts fromThe routed checkpoint of Phase A, restored or still in memory
ChangesNo intentional edit of the netlist or routing. It extracts parasitics, analyzes timing, and writes reports and caches
Ends atReport folders named after the candidate they describe

7.1  Configure extraction and the analysis

The multi-mode multi-corner (MMMC) setup comes from the project: views, libraries, RC technology and derates. It was validated when you confirmed the starting checkpoint. This block does not define it. Set the analysis type first, because SI needs it. Then set extraction and SI, then read everything back.

CONFIGURE - POST-ROUTE ANALYSIS, EXTRACTION AND SI MODES (SETTINGS ONLY)
innovus> setAnalysisMode -analysisType onChipVariation -cppr both ;# OCV, remove CPPR
innovus> setExtractRCMode -engine postRoute -effortLevel low -coupled true ;# routed RC
innovus> setDelayCalMode -SIAware true ;# include crosstalk in delay calculation
CHECK - READ THE THREE MODES BACK (ANALYSIS ONLY)
innovus> getAnalysisMode ;# read the analysis mode back
innovus> getExtractRCMode ;# read the extraction mode back
innovus> getDelayCalMode -SIAware ;# read the SI setting back

Now measure, and save what you measured.

REPORT - THE BASELINE CANDIDATE R0 (WRITES EVIDENCE FILES)
innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_route -prefix R0 ;# setup on routed wires
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_route -prefix R0 ;# hold on routed wires
innovus> saveDesign routed_R0.enc ;# save the baseline candidate

timeDesign -⁠postRoute runs the native detailed extraction itself. It does not run early global route. The expanded views give you one report per analysis view.

7.2  The baseline

Table 7 compares the start of Phase A with R0.

Table 7 Estimated wires against routed wires (invented values)
MeasureStart of Phase A (estimated wires)R0 (routed, extracted)
Setup WNS+0.040-0.085
Setup TNS and endpoints0, none-1.30, 31 endpoints
Hold WNS+0.050-0.022
Hold TNS and endpoints0, none-0.180, 12 endpoints
Max transition violatorsnot recorded in this comparison7 nets
Max capacitance violatorsnot recorded in this comparison3 nets

Everything in Phase B is measured against the R0 column. Setup and hold both went from passing to failing. The electrical counts were not recorded at the start of Phase A in this table. The post-CTS electrical reports still had to be reviewed, though. R0 is where this chapter begins counting them.

The counts in the table name different objects:

7.3  Why one path lost 0.125 ns

Let us consider the worst setup path, P1. It runs from u_acc/acc_reg_12 to u_out/res_reg_3 on clock clk_core, period 2.5 ns. The capture clock arrives at 0.650 ns and the launch clock at 0.640 ns. Setup time is 0.080 and uncertainty is 0.050, so:

EXAMPLE - REQUIRED TIME OF P1
required time = 0.650 + 2.500 - 0.080 - 0.050 = 3.020 ns

The data arrives at launch latency, plus clock-to-Q, plus the data delay: 0.640 + 0.210 + the data delay.

ILLUSTRATIVE OUTPUT - PATH 1 AFTER ROUTE (INVENTED VALUES; LAYOUT DIFFERS)
Path 1: VIOLATED Setup Check with Pin u_out/res_reg_3/D
  Launch clock latency      0.640
  Clock-to-Q                0.210
  Logic cells               1.835
  Wire (base RC delay)      0.395
  Crosstalk delta (SI)      0.025
  Arrival time              3.105
  Required time             3.020
  Slack                    -0.085

Check the arithmetic: 0.640 + 0.210 + 1.835 + 0.395 + 0.025 = 3.105. The layout of a real report differs, and the values here are invented. What matters is that you can find the same four groups in your report: cells, wire, crosstalk and the clock terms. The split of the wire term into base RC and a separate crosstalk delta is a simplified bookkeeping view.

The change from estimate to route has three parts, and each has a physical cause (Table 8).

Table 8 Where the 0.125 ns went (invented values)
PartEstimateRoutedChangeCause
Wire delay0.3300.395+0.065Length 320 um became 455 um: the straight way crosses the macro, which blocks the low routing layers, so the route goes around it
Crosstalk00.025+0.025A neighbor switches the other way over a long parallel run
Cell delay1.8001.835+0.035The weak driver sees a more resistive, more capacitive wire. Its output edge is slower, so the next cell is slower too
Total2.1302.255+0.125

A longer wire is slower for two reasons at once. Resistance grows with length, and so does capacitance. So for an isolated uniform wire, its own RC term grows faster than linearly. Buffering, loading, layer changes and coupling change the path total, so treat this as a tendency. It is one reason a detour can hurt more than its extra length suggests.

Figure 9 shows the wire part: the same net, estimated and routed.

One net, estimated and routed
A simplified straight estimate of 320 um against a routed detour of 455 um
One net, estimated and routed
Figure 9 Left: a simplified straight-line estimate of 320 um. Right: the routed detour of 455 um around the macro, whose routing obstruction blocks M3 to M6 in this example. A halo alone only keeps cells out; it does not block wires. Not to scale.

What to notice: Wire delay 0.330 became 0.395, plus 0.025 of coupling: +0.090 ns from the wire. With +0.035 from the cells, slack +0.040 becomes -0.085. Real early-route estimates can see obstacles, but still differ from final geometry.

Coupling needs its own picture, because it works in both directions. Setup analysis assumes the neighbor makes the victim slower. Hold analysis assumes it makes the victim faster. Each check must hold in its own worst case. On P1 the slow case adds 0.025 ns. On the hold pair, a same-way neighbor speeds the edge by 0.022 ns. Figure 10 shows the geometry and both effects.

Coupled neighbors
Three parallel M3 wires: a victim between two aggressors
Coupled neighbors
Figure 10 Same wires, same length, same layer: only the neighbors' switching differs. The dimension s is the spacing between neighbors. Values are the chapter's invented example.

What to notice: The victim tends to be slower when the neighbor switches the other way, and faster when it switches the same way. Setup takes the slow case and hold the fast case, when the switching windows can overlap.

Subtract the launch latency and the clock-to-Q from the required time. The rest is the data path's budget: 3.020 - 0.640 - 0.210 = 2.170 ns. Any data delay above that is negative slack.

Figure 11 puts the three versions of P1's data delay side by side against the budget.

The data delay of path P1, three times
Pre-route, routed and repaired, against a budget of 2.170 ns
The data delay of path P1, three times
Figure 11 Blue is cell delay, tan is wire delay and red is coupling. The vertical line is the budget of 2.170 ns. Values are invented.

What to notice: The routed bar crosses the budget by 0.085. The repaired bar, from "Optimize setup", is back under it.

7.4  The limits of this evidence

What the evidence proves, and what it does not

Proves: with this extraction setting and this analysis mode, the candidate has these slacks in the analyzed views. R0 is the reference that later candidates are compared with. Does not prove: that signoff timing agrees. Implementation extraction, crosstalk analysis and variation handling differ from the signoff tool's. Correlation to signoff is a separate measurement. Finishing steps (fill, decoupling cells, ECOs) can still change the wires. Does not prove: that every endpoint was analyzed. Read the coverage report beside the slacks.

Common beginner mistake

Reading only the setup WNS. A route can pass setup and fail hold in the same run, and a summary that shows only one number hides it. Read setup, hold and the electrical limits together, with coverage beside them.

8  Optimize setup

Setup repair that starts with the command instead of the diagnosis wastes runs. Four different causes can produce the same negative slack, and each has a different cheap fix. Find the cause on the worst path, then let the tool repair the rest.

8.1  Diagnose before repairing

For P1, four causes compete. Each has a check that rules it in or out (Table 9). In the checks, n_p1 is the example name of P1's long net.

Table 9 Four causes of P1's setup loss
CauseDistinguishing checkIn P1
Weak driver for its loadThe driver's output transition in the path report is high compared with its neighborsYes. Cell delay grew by 0.035, and the driver is a small size
Wire on layers that are too lowreport_net_wires -⁠net n_p1 shows the layer of each pieceYes. The long runs are on M3 and M4
DetourThe routed length (455 um) against the straight distance (320 um)Yes, but the macro blocks the straight way. This is not a setup-stage repair
CrosstalkCompare the path with and without the crosstalk termYes, 0.025. Layer choice and spacing reduce it

Two of the four are repairable at this stage: the driver and the layers. The detour stays. Moving a macro or its halo reopens two earlier stages: Placement, Pre-CTS Optimization, Checks and Handoff and Clock Tree Synthesis, Post-CTS Optimization, Checks and Handoff. Name the detour in the acceptance record instead of fighting it.

8.2  Repair

Let the tool do the general work first. It sees all violating paths, not only P1.

REPAIR - POST-ROUTE OPTIMIZATION, SETUP PRIORITY
innovus> setOptMode -opt_setup_target_slack 0.0 ;# setup target slack of 0.0 ns
innovus> optDesign -postRoute -outDir timing_route -prefix S1opt ;# post-route repair

Then raise the layer preference on what is still stubborn, and route only that net again. Clear the selection first and last.

REPAIR - RAISE THE LAYERS OF ONE STUBBORN NET (EXAMPLE LAYER NUMBERS)
innovus> setAttribute -net n_p1 -bottom_preferred_routing_layer 5 \
    -top_preferred_routing_layer 6 -preferred_routing_layer_effort high ;# prefer 5-6
innovus> deselectAll ;# start with an empty selection
innovus> selectNet n_p1 ;# select the stubborn net
innovus> detailRoute -select ;# reroute only that net
innovus> deselectAll ;# clear the selection again

A manual reroute changes the wires, so every number measured before it is out of date. Refresh the evidence before you call the result a candidate.

CHECK - FRESH EVIDENCE AFTER THE LAST PHYSICAL CHANGE (ANALYSIS ONLY)
innovus> extractRC ;# extract parasitics from the current wires
innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_route -prefix S1 ;# fresh setup numbers
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_route -prefix S1 ;# fresh hold numbers
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# recheck connectivity
innovus> verify_drc -report S1_drc.rpt ;# recheck design rules
innovus> verify_antenna -report S1_antenna.rpt ;# recheck antenna
innovus> report_constraint -all_violators > S1_constraints.rpt ;# list all violators

In this example, the two repairs on P1 save 0.115 ns (Table 10).

Table 10 The two repairs on P1 (invented values)
RepairSavesResulting delay
Driver X2 to X4 (a stronger size of the same cell)0.060cells 1.775
Long runs from M3 and M4 to M5 and M60.055wire 0.345 plus crosstalk 0.020 = 0.365
Total0.115data delay 2.140

Check: 1.775 + 0.365 = 2.140. Arrival is 0.640 + 0.210 + 2.140 = 2.990. Required is 3.020, so slack is +0.030. The difference 2.255 - 0.115 = 2.140 confirms the saving.

8.3  What this repair costs

Figure 12 shows the same routed path before and after the two repairs.

The same routed path, before and after
Left: weak driver, low layers. Right: stronger driver, wires on M5 and M6
The same routed path, before and after
Figure 12 Driver X2 to X4 saves 0.060 ns and the upper layers save 0.055 ns: 2.255 - 0.115 = 2.140. Values invented, not to scale.

What to notice: The detour around the macro is unchanged, because in this example the macro also blocks M5 and M6. Delay was recovered by driving the wire harder and moving it to faster layers.

Acceptance decision - gate after setup repair

Candidate S1 is acceptable as input to hold repair when two things are true. Setup WNS and TNS meet the project target in the analyzed views. The design-rule checks still pass on the changed nets. The fresh evidence above is what counts, not the numbers printed by the optimizer. In the example, S1 has setup WNS +0.030, TNS 0, 0 endpoints, hold -0.022, 2 transition and 0 capacitance violators.

Save only after that evidence is in hand.

SAVE - THE SETUP-REPAIRED CANDIDATE
innovus> saveDesign routed_S1.enc ;# save candidate S1

9  Hold and electrical repair

Hold repair and electrical repair both add cells. Each can take slack from setup. This section shows how, with one worked pair of paths. Then it separates electrical repair from timing repair, because they answer different questions.

9.1  Why routed wires expose hold

A hold check asks whether new data arrives too early, while the capture flop still needs the old value. The data must not arrive before the capture clock edge plus the hold time. Hold uses the minimum delay of the data path. So it is sensitive to everything that makes a path faster: shorter wires, a neighbor switching the same way, a sharper slew.

Let us consider the worst hold pair, from flop FF1 to flop FF2. It runs through a two-input AND gate, where the short FF1 path meets the long FF3 path. When the FF1 arc is timed, the FF3-side input is assumed to be 1 (non-controlling), and the other way around. So both arcs through the AND gate are timed. The gate delay is inside the path delays below. In the example, FF1 is u_acc/acc_reg_4 and FF2 is u_io/io_reg_9.

The launch clock arrives at 0.640 and the capture clock at 0.890. So the capture clock is 0.250 later than the launch clock. That skew is the reason hold is tight: data has to survive 0.250 ns of extra waiting. Hold time is 0.040 and uncertainty is 0.020, so:

EXAMPLE - REQUIRED TIME OF THE HOLD PAIR
required time = 0.890 + 0.040 + 0.020 = 0.950 ns

Table 11 shows the pair before and after routing.

Table 11 The hold pair, pre-route and routed (invented values)
TermPre-routeRouted
Clock-to-Q0.2000.200
Minimum data delay0.1600.088
Arrival (0.640 + the above)1.0000.928
Slack (arrival - required)+0.050-0.022

The minimum data delay dropped by 0.072. Three causes add up to it (Table 12).

Table 12 Why the minimum data delay dropped (invented values)
CauseAmount
The routed wire is shorter than the estimate0.030
A neighbor switching the same way speeds the victim edge0.022
Better input slew on intermediate cells, which shortens their delay (measured as a total over those cells)0.020
Total0.072

Estimates are often pessimistic about wires on short paths. Routing can remove that pessimism, which tends to help setup and hurt hold.

The 0.020 is a delay inside the path. It is not a change to the hold time of FF2. Slew at the capture pin can change the library hold requirement. That is a different term, on the required-time side, and a sharper slew does not always improve it.

Figure 13 draws the same numbers on one time axis.

The hold pair on one time axis
Launch at 0.640, capture at 0.890, required time 0.950 ns
The hold pair on one time axis
Figure 13 The capture clock is 0.250 later than the launch clock. Arrival moves from 1.000 before routing to 0.928 after it. Values are invented.

What to notice: The routed arrival lands before the required time of 0.950, so hold slack is 0.928 - 0.950 = -0.022.

9.2  The repair and what it takes from setup

The usual hold repair is a delay cell: a cell that adds delay and does nothing else. Put one in the fast corner and the pair is fixed. A delay cell of 0.050 in the fast corner gives -0.022 + 0.050 = +0.028.

However, the same cell sits where other paths share it. In this example it sits at position H1, on the net between the AND gate and FF2. The long path from FF3 also passes there. The cell is slower in the slow corner, where setup is checked: it costs 0.080 there. The long path had slack +0.075, so now it has 0.075 - 0.080 = -0.005.

Hold repair with the default settings in the tool is allowed to do this. The option that controls it is -⁠opt_hold_allow_setup_tns_degradation. Its default is true, meaning setup TNS may get worse while hold is fixed. Setting it to false protects setup TNS only. It is not a promise about setup WNS or about every path, so read the setup numbers again afterwards.

Figure 14 shows both positions of the delay cell.

A hold fix that costs setup
FF1 drives the short path and FF3 the long path; both meet at an AND gate before FF2
A hold fix that costs setup
Figure 14 Position H1 sits on the shared net after the AND gate. Position C2 sits on the FF1 branch only. The arithmetic for H1 is in the ledger. Values invented.

What to notice: One cell helps one check and costs margin in the other. A cell on a shared net is paid for by every path through it.

C2 restarts from S1, not from H1. H1 is an experiment that did not protect setup, so it is not a parent. Start a new session and restore the saved S1 checkpoint (the reason is in "Confirm the starting checkpoint"). Replay the site setup and read the analysis modes back. Database identity alone does not prove identical analysis settings.

REPAIR - POST-ROUTE HOLD REPAIR THAT PROTECTS SETUP (FRESH SESSION, FROM S1)
innovus> restoreDesign routed_S1.enc.dat stream_acc ;# restore S1 in a fresh session
innovus> source site_setup.tcl ;# replay the approved site setup
innovus> getAnalysisMode ;# read the analysis mode back
innovus> getDelayCalMode -SIAware ;# confirm SI is on
innovus> setOptMode -opt_hold_allow_setup_tns_degradation false ;# protect setup TNS
innovus> setOptMode -opt_hold_target_slack 0.0 ;# hold target slack of 0.0 ns
innovus> optDesign -postRoute -hold -outDir timing_route -prefix C2hold ;# repair hold

site_setup.tcl is the example name for the site-owned procedure. -⁠opt_hold_target_slack sets the hold target. Zero is only a starting value: write down the target your project uses, and why.

In the example, the hold repair with the default produces candidate H1. H1 has hold WNS +0.028 and TNS 0, but setup WNS -0.005, TNS -0.005 and one endpoint. Running it from S1 with the protection on leads to C2. There the cell goes at position C2, on the FF1 branch before the gate. Only the short path pays for it. C2 is a candidate only after its final state is saved and measured.

Common beginner mistake

Treating "hold met" as success without rereading setup. The two checks share cells. Always report setup and hold from the same candidate, in the same run.

9.3  Electrical repair is a separate question

Maximum transition and maximum capacitance are not timing checks. They are limits that a pin must not exceed, no matter what the slack is. A cell driving a long wire can produce a slow edge. That edge can make the next cell misbehave, even if the path meets setup. These limits are often called DRV (design rule violation) limits in optimization commands.

REPORT - ELECTRICAL VIOLATORS (PRE-DRV STATE OF C2)
innovus> report_constraint -drv_violation_type {max_transition max_capacitance} \
    -all_violators > C2hold_electrical.rpt ;# transition and capacitance violators

Reports go to the log or the screen unless you redirect them. A redirect overwrites an existing file, so name each state's file yourself.

ILLUSTRATIVE OUTPUT - THE SAME REPORT ON R0 (INVENTED VALUES)
max_transition   n_4412  limit 0.300 actual 0.342 slack -0.042 VIOLATED
max_capacitance  n_6035  limit 0.080 actual 0.091 slack -0.011 VIOLATED

R0 has 7 transition and 3 capacitance violators. The excerpt above stands for R0, not for C2hold. Setup repair fixes most of them as a side effect. The cause is often the same: a weak driver on a long wire.

S1 has 2 transition and 0 capacitance violators. The two remaining transition violators need a different repair, because their cause is not delay. In this example the hold cells add no new capacitance violation. The default optDesign -⁠postRoute also repairs design-rule violations, so your own counts can differ.

optDesign -⁠postRoute -⁠drv fixes only maximum capacitance and maximum transition. It does not repair setup or hold, and it is not allowed with -⁠incr.

REPAIR - ELECTRICAL LIMITS ONLY (CONTINUES THE C2 SESSION)
innovus> optDesign -postRoute -drv -outDir timing_route -prefix C2drv ;# tran and cap

The two prefixes, C2hold and C2drv, keep the two stages' reports apart. Why a separate stage? It targets exactly two limits, and it is not a setup or hold repair. So after it, you read setup, hold and the electrical counts again from the same state. Do not assume that fixing one set leaves the other alone.

Takeaway Hold uses the minimum delay and setup the maximum, so a repair that adds delay helps one and spends the other. A cell on a shared net is paid for by every path through it. Electrical limits and slacks are independent checks. The order setup, hold, electrical is a reasonable default, not a universal one: measure after each step and be ready to loop.

10  Reroute, re-extract and repeat

Every repair changes the database, and every change needs a fresh measurement. The way to stay in control is to treat each repair as a candidate. A candidate is a saved database with its own reports, compared with the one before. A repair that makes the next number worse is discarded, not patched on top.

10.1  What a repair leaves behind

Repairs add or change cells and wires. The optimizer routes its own changes. You must still check three things after each one:

10.2  One compact comparison

Table 13 puts the four candidates side by side.

Table 13 Candidates of the example (invented values)
CandidateWhat produced itSetup WNS / TNS / endpointsHold WNS / TNS / endpointsMax tranMax cap
R0Route, extract-0.085 / -1.30 / 31-0.022 / -0.180 / 1273
S1R0, setup repair+0.030 / 0 / 0-0.022 / -0.180 / 1220
H1S1, default hold repair-0.005 / -0.005 / 1+0.028 / 0 / 020
C2S1, protected hold repair, -⁠drv, fresh evidence+0.012 / 0 / 0+0.025 / 0 / 000

Read it row by row.

That is a trade, and it is visible because the candidates were kept. Figure 15 draws the same history as a tree.

Before you save C2, produce its fresh evidence. Run the C2 reports of "Reporting: timing, electrical, rules and connectivity", then save.

One candidate per step
R0 to S1, then a fork: H1 (discarded) and C2, both from S1
One candidate per step
Figure 15 Each box is a saved candidate with its own reports. H1 is a discarded experiment. C2 forks from S1 and is saved and measured after its final checks. WNS in ns, values invented.

What to notice: C2 is not a child of H1. It is a separate branch of S1.

SAVE - THE FINAL C2 STATE, AFTER ITS C2 REPORTS
innovus> saveDesign routed_C2.enc ;# save candidate C2

10.3  Which saved state does each experiment start from?

Table 14 The parent of each experiment
ExperimentStarts from
First setup repairR0, the routed and extracted baseline
Hold repairThe setup-repaired candidate of the same experiment, restored in a fresh session
A different option setThe same parent, restored in a fresh session, not the child of the last try
A change in placement or clockThe placement or clock tree stage, re-accepted there

10.4  When to stop

Stop repairing and investigate upstream when:

The last case is common. If every remaining setup violator crosses the same macro channel, the repair is in floorplan or placement. It is not necessarily in a fourth optDesign run.

Stop and investigate

11  Reporting: timing, electrical, rules and connectivity

Each decision in this chapter rests on a report, and each report answers one question. Reports come before debugging for two reasons. You cannot debug a symptom you have not read correctly. And most debugging starts with the question "which report is that number from?".

Run the reports on the candidate in memory, or restore the candidate you saved first. Name the candidate in your notes. Table 15 maps each question to its report family.

Table 15 One question per report family
QuestionReport familyNative command
Were the required views active, and are the constraints complete?Views and completenessall_analysis_views, check_timing
Does timing meet its targets?Timingreport_timing, timeDesign -⁠postRoute
Which endpoints were actually analyzed?Coveragereport_analysis_coverage
Do transition and capacitance limits hold?Electricalreport_constraint
Is the geometry legal, connected and antenna-clean?Rules and connectivityverify_drc, verifyConnectivity, verify_antenna
Is the clock still as built?Clockreport_clock_timing

11.1  Views and constraint completeness

Question. Did the required views run, and does every necessary constraint exist?

CHECK - ACTIVE VIEWS AND CONSTRAINT COMPLETENESS (FINAL CANDIDATE)
innovus> all_analysis_views -type setup ;# list the active setup views
innovus> all_analysis_views -type hold ;# list the active hold views
innovus> check_timing -verbose > C2_check_timing.rpt ;# constraint completeness

11.2  Timing

Question. Does each path meet setup and hold, with the real wires?

REPORT - TIMING SUMMARY AND PATHS (WRITES EVIDENCE FILES)
innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_final -prefix C2 ;# final setup summary
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_final -prefix C2 ;# final hold summary
innovus> report_timing -late -max_paths 5 -nworst 1 > C2_setup_paths.rpt ;# setup paths
innovus> report_timing -early -max_paths 5 -nworst 1 > C2_hold_paths.rpt ;# hold paths
ILLUSTRATIVE OUTPUT - CANDIDATE C2 SUMMARY (INVENTED VALUES; LAYOUT DIFFERS)
Setup      WNS +0.012         TNS 0.000       Violating endpoints 0
Hold       WNS +0.025         TNS 0.000       Violating endpoints 0

11.3  Coverage

Question. How many checks were analyzed, and why were the rest not?

REPORT - ANALYSIS COVERAGE OF THE FINAL CANDIDATE (WRITES EVIDENCE FILES)
innovus> report_analysis_coverage -verbose {violated untested} -sort reason \
    > C2_coverage.rpt ;# met, violated and untested checks
ILLUSTRATIVE OUTPUT - CANDIDATE C2 COVERAGE (INVENTED VALUES; LAYOUT DIFFERS)
Check type       Total     Met     Violated   Untested
Setup            4020      4002         0         18
Hold             4020      4008         0         12

11.4  Electrical limits

REPORT - ELECTRICAL VIOLATORS (WRITES EVIDENCE FILES)
innovus> report_constraint -drv_violation_type {max_transition max_capacitance} \
    -all_violators > C2_electrical.rpt ;# final transition and capacitance violators

The excerpt is in "Hold and electrical repair". The file name is explicit because the report otherwise goes to the log. This name, C2_electrical.rpt, is reserved for the final C2 state.

11.5  Rules and connectivity

REPORT - RULES, CONNECTIVITY AND ANTENNA ON THE CANDIDATE (WRITES EVIDENCE FILES)
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# opens and unrouted nets
innovus> verify_drc -report C2_drc.rpt ;# design rules of candidate C2
innovus> verify_antenna -report C2_antenna.rpt ;# antenna of candidate C2
ILLUSTRATIVE OUTPUT - CANDIDATE C2 CHECKS (INVENTED VALUES; LAYOUT DIFFERS)
verifyConnectivity         Open 0      Unrouted 0
verify_drc                 Total 0
verify_antenna             Total 0

11.6  Clock

REPORT - CLOCK SKEW FOR THE HOLD CHECK (EXAMPLE VIEW NAME)
innovus> report_clock_timing -type skew -early -view hold_view \
    > C2_clock_skew.rpt ;# clock skew for the hold check

report_clock_timing -⁠type skew defaults to the setup skew. For the hold check, ask for the early side and name the hold view. Restrict it to the intended start and end pair with the options your release supports.

EXAMPLE - SKEW BOOKKEEPING (CHAPTER CONVENTION, NOT A TOOL LAYOUT)
launch clock arrival   u_acc/acc_reg_4     0.640
capture clock arrival  u_io/io_reg_9       0.890
s = capture - launch = +0.250
REPORT - CLOCK WIRES AND VIAS OF THE FINAL CANDIDATE (EXAMPLE NET NAMES)
innovus> report_net_wires -net clk_core_trunk1 -file C2_wires_trunk1.rpt ;# trunk 1
innovus> report_net_wires -net clk_core_trunk2 -file C2_wires_trunk2.rpt ;# trunk 2
innovus> report_via -on_clock_nets -detail ;# via details on clock nets

Repeat report_net_wires for every net on the intended clock-net list, not for one sample. Compare the rule and layer policy with the post-CTS record. Approved changes are acceptable if they are documented. Literal geometric identity is not required.

11.7  Recognizing a stale report

A stale report describes a database that no longer exists. It looks like any other report. Check these signs before you trust a number. They are triggers for investigation, not proof. Tie freshness to the last change that matters (geometry, netlist, constraints or analysis settings), and to the candidate and configuration identity.

Common beginner mistake

Comparing the slack of today's candidate with a number copied from a log three hours ago. Rerun the report on the saved candidate, and compare two reports, not a report and a memory.

12  Debug common failures

Routing and post-route failures are cheap to fix when the cause is known, and expensive when it is guessed. Every case here uses the same six steps, shown in Figure 16:

  1. Symptom: one named failure.
  2. Evidence: the report or view that shows it.
  3. Competing causes: at least two, written down.
  4. Distinguishing check: one look that rules a cause in or out.
  5. Repair: only the confirmed cause.
  6. Remeasure: rerun the same report, with the same settings, on the new candidate.
The debug order
Six steps in a fixed order, with one return path
The debug order
Figure 16 If the symptom remains, restore the saved candidate in a fresh session, return to step 1 and write the causes down again.

What to notice: The repair comes fifth. A repair before the distinguishing check is a guess.

12.1  Case 1: persistent congestion or incomplete routing

12.2  Case 2: recurring design-rule violations

CHECK - CASE 2: ASK FOR NDR SPACING EXPLICITLY
innovus> verify_drc -check_ndr_spacing -report case2_ndr.rpt ;# include NDR spacing

12.3  Case 3: opens and shorts

CHECK - CASE 3: WHICH NETS ARE PRESERVED?
innovus> report_preserves -obj_type net -dont_touch ;# explicit net preservation
innovus> report_preserves -obj_type net -dont_touch -computed ;# include inherited ones

12.4  Case 4: antenna violations that stay

CHECK - CASE 4: ONE NET IN DETAIL
innovus> verify_antenna -nets n_7781 -detailed -report antenna_n_7781.rpt ;# one net

12.5  Case 5: setup degrades after route

12.6  Case 6: hold exposed by routed parasitics

12.7  Case 7: setup regression after hold repair

12.8  Case 8: transition or capacitance violations

12.9  Case 9: timing stops improving

12.10  Case 10: reports that do not match the candidate

13  Accept the candidate and hand it to finishing

A candidate that was repaired is not necessarily one that can go forward. No command knows your project's margins, its waivers, or what finishing will do next. The decision uses evidence, and it ends in one of three states.

13.1  Five assessments, kept independent

A pass in one assessment never offsets a failure in another. Good setup does not cancel an open net. Table 16 lists the five.

Table 16 The five assessments
#Assessment and native evidenceReady meansDo not hand off when
1Connectivity and rules. verifyConnectivity, verify_drc, verify_antennaNo open, unrouted net or short; rule and antenna violations repaired or documentedAn open, unrouted net or short remains
2Timing. timeDesign -⁠postRoute, report_analysis_coverageTargets met in every required view; untested checks explainedA required view did not run, or an untested check has no reason
3Electrical limits. report_constraintLimits met, or each violator documentedA violator has no reason on record
4Clock routes. report_net_wires, report_via -⁠on_clock_nets, report_clock_timingClock rules and layers as set at clock tree synthesisA clock net lost its rule or layer
5Candidate and record. Saved checkpoint, matching reports, handoff noteThe saved candidate is the one reviewedReports are stale, or the candidate name is unclear

13.2  Three states

The five assessments roll up into one of three states, drawn in Figure 17.

Three acceptance states
Clean, accepted with documented exceptions, and not ready
Three acceptance states
Figure 17 Each state says what was checked and what happens next, with an example from this chapter.

What to notice: Each state carries text as well as color. "Accepted" is not "clean".

The thresholds that turn a number into a pass belong to your project. This chapter does not set any.

13.3  Worked example: candidate C2

C2 has setup WNS +0.012, hold WNS +0.025, and zero transition and capacitance violators. Connectivity, rules and antenna are clean. Coverage shows 18 untested setup checks and 12 untested hold checks.

Both records depend on the receiving project's stage target. This example assumes a target of 0.000 ns for setup and hold at this stage. That is an invented value, not a recommendation, and acceptance is conditional on the real target.

Table 17 The two exception records of C2
ItemEvidenceOwner and approvalReason acceptable nowRecheck
18 setup and 12 hold checks untested (the exact check and object list is attached, with mode, view and reason code)report_analysis_coverage sorted by reason, C2_coverage.rptConstraint owner, approval reference and date recordedCapture clocks tied off in this mode, and the function is covered in the other required modesWhen modes or constraints change
P1 slack +0.012, thinPath report of C2Timing owner, approval reference and date recordedMeets the stated stage targetAfter fill, and again against signoff

Open nets, shorts and a missing required analysis are not waivable under this chapter's gate. An inherited waiver counts only if it is current, approved and still applicable.

13.4  Save and export what finishing needs

The native checkpoint is the authoritative restart artifact. The netlist and the DEF (design exchange format) file are exchange forms for tools that cannot read it. Use your own names. Say what each file does and does not carry, because the receiving flow depends on it.

SAVE - THE HANDOFF CANDIDATE AND ITS EXCHANGE FILES (EXAMPLE NAMES)
innovus> saveDesign handoff_route.enc ;# native checkpoint for restart
innovus> saveNetlist handoff_route.v ;# logical Verilog netlist
innovus> defOut -routing handoff_route.def ;# DEF with routing

Then regenerate the evidence from the saved candidate, so the reports and the checkpoint cannot disagree. Start a new Innovus session first, because the tool does not load a second database while a design is in memory. Name every file for the candidate.

REPORT - FINAL EVIDENCE FROM THE SAVED CANDIDATE (FRESH SESSION, PART 1)
innovus> restoreDesign handoff_route.enc.dat stream_acc ;# restore the handoff candidate
innovus> source site_setup.tcl ;# replay the approved site setup
innovus> getAnalysisMode ;# read the analysis mode back
innovus> getExtractRCMode ;# read the extraction mode back
innovus> getDelayCalMode -SIAware ;# confirm SI is on
innovus> all_analysis_views -type setup ;# active setup views
innovus> all_analysis_views -type hold ;# active hold views
innovus> check_timing -verbose > handoff_check_timing.rpt ;# constraint completeness
REPORT - FINAL EVIDENCE FROM THE SAVED CANDIDATE (PART 2)
innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_handoff -prefix handoff ;# setup on the handoff candidate
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_handoff -prefix handoff ;# hold on the handoff candidate
innovus> report_constraint -all_violators > handoff_constraints.rpt ;# all violators
innovus> report_analysis_coverage -verbose {violated untested} -sort reason \
    > handoff_coverage.rpt ;# coverage with reasons
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# connectivity
innovus> verify_drc -report handoff_drc.rpt ;# design rules
innovus> verify_antenna -report handoff_antenna.rpt ;# antenna
innovus> report_net_wires -net clk_core_trunk1 -file handoff_wires_trunk1.rpt ;# clock
innovus> report_net_wires -net clk_core_trunk2 -file handoff_wires_trunk2.rpt ;# clock
innovus> report_via -on_clock_nets -detail ;# clock vias
innovus> report_clock_timing -type skew -early -view hold_view \
    > handoff_clock_skew.rpt ;# hold-side clock skew

The broad report_constraint -⁠all_violators also lists special checks, and its file is named for what it holds. Repeat report_net_wires for the whole intended clock-net list, because post-route optimization can change clock wires. Read the handoff files, not the intermediate ones.

13.5  The handoff note

The note separates what is established from what is still provisional (Table 18).

Table 18 The handoff note
EstablishedProvisional
Wires are connected and rule-clean in the session technologySignoff extraction and timing have not been run
Setup and hold meet the project targets in the analyzed views, on implementation extraction, with coverage and its untested checks explainedFill, decoupling cells and later ECOs can change wires and slacks
Electrical limits are metOpen items and their owners, as in the exception records

13.6  The package manifest

The handoff note says what is established. A receiver also needs to tie the files and claims together without asking you. Attach a compact manifest (Table 19).

Table 19 The package manifest
ItemWhat to record
Tool and top cellTool build, startup scripts, top cell name
CandidateSaved checkpoint directory, restore command, candidate name (here handoff_route.enc)
DependenciesLibrary, LEF, SDC and technology paths, or immutable versions or hashes
ConfigurationThe site setup script and its version, required and active views, extraction, SI and variation settings
EvidenceThe exact report files (handoff_*, C2_*), with their folders
Targets and exceptionsThe stage targets used, and the exception records with approval references
Export policyWhich of physical-only instances, power-ground connections and shields the netlist and DEF carry
Receiver checksWhat the receiver must re-run before relying on the package
What the evidence proves, and what it does not

Proves: the saved candidate has these results, in these views, with this extraction. Does not prove: signoff closure. Finishing can reopen timing. Fillers and decoupling cells change the layout, metal fill adds coupling capacitance, and an ECO changes wires. After any of them, run the checks of this chapter again on the new candidate.

14  Before you copy any recipe

This chapter says which commands it uses, and it also says that none of them was run. A reader on a different release needs to know what each claim is, and what to try before trusting a recipe.

14.1  Commands by recipe

Table 20 maps each recipe in this chapter to the commands to confirm with -⁠help in your installation.

Table 20 Commands to confirm for each recipe
RecipeCommands to confirm
Restore and saverestoreDesign, saveDesign, saveNetlist, defOut
Layer bounds and attributessetDesignMode, setAttribute, getDesignMode, getAttribute
Router modessetNanoRouteMode, getNanoRouteMode, routeDesign, globalRoute, detailRoute, ecoRoute
CongestionreportCongestion, dumpNanoCongestArea
ChecksverifyConnectivity, set_verify_drc_mode, verify_drc, verify_antenna, report_preserves
Timing and optimizationsetAnalysisMode, setDelayCalMode, setExtractRCMode, timeDesign, optDesign, setOptMode, check_timing, all_analysis_views
Reportsreport_timing, report_constraint, report_analysis_coverage, report_clock_timing, report_net_wires, report_via, report_route

14.2  Three kinds of statement

Three kinds of statement are mixed in this chapter. Keep them apart.

14.3  The smoke test

Do these in a licensed, approved environment, and record what happens.

  1. Check each command and option you will use with -⁠help in your installation, and record the build.
  2. Restore a disposable copy of an accepted checkpoint in a fresh session. Confirm that every example name (net, layer, cell, view, file name) maps to a real object, and that all dependencies resolve.
  3. Try the split globalRoute and detailRoute path, and the routeDesign-only clock settings, separately. Do not infer one command's behavior from another's name.
  4. Reproduce the congestion intervention under your real layer bounds. Look at the physical result, not the invented numbers.
  5. Try an isolated selected-net reroute, a marker-driven repair and a one-net antenna report. Look for collateral changes.
  6. Run one candidate through the site configuration before and after a save and restore, and reconcile the results.
  7. Check the final report, database, netlist and DEF package from the receiving side.
  8. Keep the logs, report files, configuration and approvals.

You do not need to reproduce the chapter's invented numbers. Report what actually happened.

End of Phase B - optimized candidate saved The candidate has been routed, extracted, optimized for setup, hold and electrical limits, reported with its evidence, and classified. Proceed to finishing with the handoff note and the saved checkpoint handoff_route.enc.

15  Common mistakes and how to catch them

Most failures at this stage are reading failures, not tool failures. The list in Table 21 collects the ones this chapter warns about, and how to catch each.

Table 21 Common mistakes at the routing stage
SymptomLikely causeFix
Overflow persists after raising router effortThe cause is capacity, such as a stale blockage, not effortCount capacity by layer; remove a confirmed blockage with its owner's approval
verify_antenna reports nothing on a new technologyNo antenna data in the LEF, so nothing was checkedConfirm the LEF antenna data before calling the result clean
verifyConnectivity lists exactly 50 errorsThe -⁠error 50 cap hides a longer listRead it as "at least 50" and raise the cap or fix and rerun
ecoRoute -⁠fix_drc reports an errorOpen nets exist, or the markers are staleSettle connectivity first and rerun verify_drc to make fresh markers
The same DRC markers return after every repairA rule the router cannot meet in that space, or a pin it cannot reachCheck NDR clustering with verify_drc -⁠check_ndr_spacing; change the rule or placement with the owner
Setup passes, but the candidate fails later on holdOnly the setup WNS was readRead setup, hold and electrical limits together, with coverage
Hold is fixed and a setup path now failsA delay cell on a shared net, with setup protection offRestart from S1 with -⁠opt_hold_allow_setup_tns_degradation false
Slack improved "too well" after a diagnosticSI was left off after a crosstalk-off runRead getDelayCalMode -⁠SIAware, restore the setting, regenerate reports
A slack cannot be reproducedA stale report, wrong prefix, or different viewsRestore the saved candidate in a fresh session, replay site setup, rerun
Clock skew looks fine, but clock wires changedSkew does not prove wire layers, widths or shieldsRerun report_net_wires and report_via -⁠on_clock_nets on the final candidate

16  Interview preparation

Beginner
Q1. What is the difference between global route and detailed route?

Global route assigns each net to a guide of gcells; detailed route draws the real wires and vias on tracks.

What is being tested: whether you separate a plan from the built result.
Beginner
Q2. How is overflow on a gcell edge computed?

Overflow = max(0, demand - capacity), counted per layer, with the positive overflows added up.

What is being tested: whether you can reduce congestion to a simple count.
Intermediate
Q3. Global route shows overflow in a channel between two macros. What do you do first?

Count the capacity by layer, so you know whether the cause is low capacity or high demand.

What is being tested: diagnosis before repair, and knowing which stage owns each cause.
Beginner
Q4. What is an antenna violation, and how can the router fix it?

Manufacturing charge on a long wire that can damage a connected gate; the router fixes it by layer hopping or a diode.

What is being tested: the mechanism, both fixes and their costs, and the data prerequisite.
Intermediate
Q5. verifyConnectivity printed exactly 50 errors. What does that tell you?

At least 50 errors exist, because -⁠error 50 caps the listing.

What is being tested: whether you know the limits of a report before you quote it.
Intermediate
Q6. Why did setup path P1 lose 0.125 ns after routing?

Three physical effects: a longer wire (+0.065), crosstalk (+0.025) and slower cells driving the heavier wire (+0.035).

What is being tested: whether you can split a slack change into causes with numbers.
Intermediate
Q7. Why can routing turn a passing hold path into a failing one?

Hold uses the minimum delay, and routing can remove pessimism that made short paths look slow.

What is being tested: understanding that setup and hold see opposite worst cases.
Advanced
Q8. A hold repair fixed hold but broke a setup path. What happened, and how do you redo it?

The delay cell sat on a net shared with a long setup path, and setup protection was off by default.

What is being tested: shared-net cost, the protection option and its limits, and restarting from the right parent.
Intermediate
Q9. Why does each experiment restart from a saved parent in a fresh session?

Because a failed experiment is not a parent, and the tool does not load a second database while one is in memory.

What is being tested: candidate discipline and why a clean starting state matters.
Advanced
Q10. What does optDesign -⁠postRoute -⁠drv repair, and why run it as its own stage?

Only maximum capacitance and maximum transition; it does not repair setup or hold.

What is being tested: knowing the scope of a repair command and remeasuring after it.
Advanced
Q11. A coverage report shows 18 untested setup checks. Is the design passing those checks?

No: untested means no result exists, so each untested check needs a reason on record.

What is being tested: reading coverage beside slack, and the meaning of "untested".
Intermediate
Q12. How do you recognize a stale report?

Check its time, its name or prefix, when extraction ran, and which views it covers.

What is being tested: evidence hygiene before you trust a number.
Beginner
Q13. What are the three acceptance states for a routed candidate?

Clean, accepted with documented exceptions, and not ready.

What is being tested: whether you treat acceptance as an evidence-based decision.

Compact glossary

Table 22 Compact glossary
TermMeaning
TrackAn evenly spaced line in a layer's preferred direction, one wire wide
Preferred directionThe direction (horizontal or vertical) most wires on a layer run
ViaA cut with metal enclosure on two adjacent layers that joins them
GcellA rectangular global routing cell; global route assigns nets to gcells
GuideThe set of gcells a net will pass through; a plan, not metal
CapacityThe number of tracks that can cross a gcell edge on usable layers
DemandThe number of wires that want to cross a gcell edge
Overflowmax(0, demand - capacity), added up over layers
NDRNon-default rule: wider wires or more spacing for selected nets, such as clocks
Route blockageA region where tracks are removed from routing
Antenna violationManufacturing charge on a long wire that can damage a connected gate
Layer hoppingMoving a long run to a higher layer to fix an antenna violation
DRC markerA design-rule violation location left by verify_drc
Open / shortA net with a missing piece / two nets touching
ExtractionTurning drawn wires into resistance and capacitance
SISignal integrity: crosstalk effects included in delay calculation
OCV / CPPROn-chip variation analysis / removal of common clock-path pessimism
WNS / TNSWorst negative slack / total of the worst negative slack per endpoint
CoverageHow many timing checks were met, violated or untested
DRVDesign rule violation limits: maximum transition and maximum capacitance
Delay cellA cell that only adds delay, used for hold repair
CandidateA saved database with its own named reports (R0, S1, C2)
Stale reportA report that describes a database that no longer exists
Exception recordItem, evidence, owner, reason, approval and recheck point for an open item

Routing and post-route on one page

Table 23 is the stage in one table. Pair it with Figure 1.

Table 23 Routing and post-route at a glance
StepMain commandsEvidence to keepGate
Confirm the startrestoreDesign, source site_setup.tcl, check_design -⁠type route, timeDesign -⁠postCTSRequired vs active views, starting slacksNothing in the "Blocks" rows
ConfiguresetDesignMode, setAttribute, setNanoRouteMode, gettersSettings printed into the logEvery setting read back
Global routeglobalRoute, reportCongestion -⁠overflowOverflow per gcell, capacity by layerNo significant overflow
Detailed routedetailRoute, ecoRoute -⁠fix_drc, detailRoute -⁠selectConnectivity, DRC, antenna, clock wires0 opens, rules clean, routed.enc saved
Extract and assesssetExtractRCMode, timeDesign -⁠postRouteR0 setup, hold, electricalBaseline saved as R0
RepairoptDesign -⁠postRoute, -⁠hold, -⁠drvFresh evidence per candidateMeets its gate; all checks re-read
Report and acceptreport_analysis_coverage, report_constraint, report_clock_timingNamed reports from the saved candidateClean, or accepted with records
Hand offsaveDesign, saveNetlist, defOut -⁠routingHandoff note and manifestReports match the checkpoint

Where the next chapter goes, and why

You now hand finishing a routed, extracted and optimized candidate with named evidence. Finishing then adds what this stage left out: fillers, decoupling cells and metal fill, and the signoff checks.

Each of those changes the layout. Fill adds coupling capacitance, and fillers and decoupling cells change the rows. So the next chapter, Chip Finishing and Signoff Handoff, reruns the same evidence discipline on a new candidate. The habits you built here carry straight over. Save a named candidate and measure it fresh. Read each report for what it does not prove, and decide with a record.