Chip Finishing and Signoff Handoff: finish, measure, verify and export

Why this chapter matters in a real project

The routed design from Routing, Post-Route Optimization, Checks and Handoff connects, obeys the router's rules and meets timing. A foundry will still not manufacture it. The cell rows have gaps, and large areas of the metal layers are nearly empty. Both are manufacturing problems, not logic problems.

Finishing fixes them, and that changes the layout the timing numbers described. Finishing is not cosmetic. It changes the physical design and can change its electrical behavior. So it must end with fresh evidence tied to the exact layout being handed off.

Prerequisites

• Understanding the Innovus Environment and Session: you start fresh sessions, restore checkpoints and read logs.
• Design Data Import, Sanity Checks and Export: you know analysis views and the site setup script.
• Floorplanning and Power Planning: you know end caps, well taps, rails and global power connection rules.
• Routing, Post-Route Optimization, Checks and Handoff: you have the accepted routed candidate and its handoff note.
• You do not need to know how a polishing machine or a fill engine works inside.
• You do not need to have run a signoff extraction before.

Learning objectives

1. Explain what finishing adds to a routed database, and why a clean routed candidate is not yet a finished one.
2. Restore the incoming candidate in a fresh session with its analysis setup, and record which layout it is.
3. Inspect the physical-only cells, complete only what is missing, and verify the result without deleting what the design needs.
4. Explain why metal fill exists and what it costs, and tell native fill, integrated signoff fill and external signoff tools apart.
5. Compute a window density by hand, then configure, insert and inspect signoff fill.
6. Re-extract with the fill present, compare against a controlled baseline, and attribute a timing change to its cause.
7. Repair a fill-related regression with a scoped, measured edit that does not break density.
8. Verify the finished layout with separate questions, export it, and write a handoff record. Every check in it is run, or marked not run.

Figure 1 shows the whole chapter as one flow. Come back to it whenever you lose your place.

Chip finishing on one page

From the accepted routed candidate to a packaged, recorded layout

What to notice: Phase A ends with F2 saved but not yet measured. Phase B measures it, repairs it into F3, and verifies and exports F3 only.

Before you start: the example design

Routing is not repeated here. The note that came with C2 is the handoff note. In this chapter, "the routed handoff" means C2 and that note together.

Time is in ns, distances in µm and capacitance in fF unless a table says pF. Cell names, layer names, rule files, map files, window sizes and every limit are example values. Use the ones from your technology and your project.

1  Scope and the incoming candidate

The routed layout is legal for the router, but not yet for the foundry. Every step in this chapter follows from one sentence. Finishing changes the layout, so it must end with fresh evidence tied to the layout handed off.

1.1  What finishing adds, and where the chapter stops

All three change the layout, so each needs its own evidence. Metal fill is the one most likely to move timing, because it adds coupling next to your wires.

The chapter produces a finished layout and evidence tied to it. Signoff verification belongs to the receiving team's tools. Examples are a foundry-deck design-rule check, a layout-versus-schematic comparison and a full signoff timing run. Where this chapter runs a native check, the text says what that check does not prove.

1.2  Which layout is which

A rejected experiment is never a parent. If an idea fails, return to the last accepted candidate in a fresh session. Start the next idea from there. The section "Verify the finished candidate" draws this lineage together with the reports each candidate owns.

1.3  Restore the incoming candidate

Finishing edits a design that somebody else accepted. A mistake in the incoming candidate costs more after fill than before it. So we restore first, then verify.

innovus> restoreDesign handoff_route.enc.dat stream_acc ;# load C2 into a new session

innovus> source site_setup.tcl ;# views, derates and tool modes (example name)
innovus> getAnalysisMode ;# show the timing analysis mode
innovus> getExtractRCMode ;# show the extraction settings
innovus> getDelayCalMode -SIAware ;# show whether delay calc is signal-integrity-aware
innovus> all_analysis_views -type setup ;# list the active setup views
innovus> all_analysis_views -type hold ;# list the active hold views
innovus> getFillerMode ;# show how filler will be added
innovus> get_verify_drc_mode ;# show what the rule check will look at
innovus> get_metal_fill_signoff_mode ;# show the fill settings, empty for now

A setting you did not expect is a finding, not a detail.

innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_F0 -prefix F0 ;# setup timing of F0
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_F0 -prefix F0 ;# hold timing of F0
innovus> report_constraint -drv_violation_type {max_transition max_capacitance} \
    -all_violators > F0_electrical.rpt ;# transition and capacitance violators
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# opens and unrouted nets
innovus> verify_drc -report F0_drc.rpt ;# native rule check

Setup               WNS +0.012   TNS 0.000   Violating endpoints 0
Hold                WNS +0.025   TNS 0.000   Violating endpoints 0
Electrical          max_transition 0         max_capacitance 0
verifyConnectivity  Open 0       Unrouted 0
verify_drc          Total 0

If a number differs, stop. Compare the active views with the project's required views first. A different view set is a more common cause than a different layout.

innovus> saveDesign fin_F0.enc ;# checkpoint F0

2  Complete the physical-only cells

Fill and checks both read the layout as it is. Suppose the rows still have gaps when you insert metal fill, and a later step fills the gaps. Then the layout you measured is not the layout you ship. Settle the cells first.

2.1  What physical-only cells are, in plain English

Figure 2 shows one row before and after filler.

One cell row before and after filler

Same row, same cells, same coordinates

What to notice: The rails and the well stripe break at both gaps in the top row and run unbroken in the bottom row. The tap and the end caps were already there.

2.2  Inspect first

innovus> checkFiller -file F0_filler_gaps.rpt ;# count core gaps that have no filler
innovus> verifyEndCap -report F0_endcap.rpt ;# end caps present and of the right type
innovus> verifyWellTap -report F0_welltap.rpt ;# well taps present and within spacing

checkFiller     Total number of gaps found: 118750
verifyEndCap    Violations 0   (end-cap cells 1280)
verifyWellTap   Violations 0   (well-tap cells 9840)

Those gaps need filler, if the project's policy is to add filler in finishing. If the project leaves filler to the receiving team, record the gap count in the handoff note. Save F1 anyway, as shown later, so every later step has one checkpoint name to restore.

2.3  Complete the filler

Before you add filler, make sure the filler cells will connect to the supply nets. addFiller uses the global power connection rules of the session to decide that. The rules come from the floorplan, and the recommended order is globalNetConnect before addFiller.

innovus> setFillerMode -core {FILLER8 FILLER4 FILLER2 FILLER1} ;# example cell names
innovus> getFillerMode ;# read the filler settings back

innovus> addFiller -prefix FIN_FILL -markFixed ;# fill every gap, lock the new filler
innovus> verify_drc -report F1_drc_first.rpt ;# first rule check after filler

• -⁠prefix FIN_FILL replaces the default prefix FILLER.
• -⁠markFixed places the new filler in fixed status, so a later optimization cannot move it. Use it when the project wants fillers locked.

innovus> addFiller -fixDRC -prefix FIN_FILL ;# replace the filler cells that cause them

-⁠fixDRC replaces the filler cells that cause the marked violations. It does not repair violations that belong to routed nets. Reroute those nets instead.

2.4  Verify the cells

innovus> checkFiller -file F1_filler_gaps.rpt ;# gaps left after filler
innovus> verifyEndCap -report F1_endcap.rpt ;# end caps still legal
innovus> verifyWellTap -report F1_welltap.rpt ;# taps still legal
innovus> verifyConnectivity -type all -error 50 -warning 50 ;# opens and unrouted nets
innovus> verify_drc -report F1_drc.rpt ;# native rule check of F1

checkFiller         Total number of gaps found: 0
verifyEndCap        Violations 0
verifyWellTap       Violations 0
verifyConnectivity  Open 0    Unrouted 0
verify_drc          Total 0
Instances           std 128610  tap 9840  endcap 1280  filler 213750  total 353480

These checks say the rows are complete in the checked area, and that no new rule violation appeared. They do not say the supply connections of the filler are right. That is a separate connectivity question. Nor do they say the implant and well rules of the foundry deck pass, which is a signoff question. Filler has no logic, but it changes the layout, so timing is read again later.

innovus> saveDesign fin_F1_cells.enc ;# checkpoint F1

F1 is now the parent of everything that follows. If nothing was added, F1 has the layout of F0, and the save still gives later steps one name to restore.

3  Metal fill: manufacturing and electrical effects

A layer of metal wiring is built by depositing metal over a patterned surface and then polishing it flat. How flat it ends up depends on how much metal each area holds. Fill exists to reduce that difference.

Fill is real metal, though. It couples to your wires, and capacitance is delay. You are adding something to a design whose timing you just accepted. So you need to know why it is there and what it does.

3.1  Why a layer needs metal that carries no signal

After metal is deposited, the surface is ground flat by chemical-mechanical polishing (CMP). A pad rubs the surface and removes material. How fast it removes it depends on how much of each material is under it.

The word to keep in mind is thickness. Where the metal is thinner, a wire is more resistive. Where the surface is uneven, the next layer starts from an uneven base. Extreme dishing or erosion can cause shorts or opens. Each effect's size depends on the process, so the numbers below are invented.

The difference is 1.9 ps. That is 15.8% of the +0.012 ns slack of C2 on P1, from one net and one cause. It is a scale estimate, not a delay model. It shows why a thin slack and a manufacturing effect belong together. Figure 3 shows both effects in a side view.

A cross-section of polishing results

Side view of metal layer M3 over dielectric, along one cut line

What to notice: The dashed line is the ideal flat level. Without fill, the wide line and the dense array sit below it; with fill, both sit much closer to it.

The rule values, window size, and minimum and maximum density come from the foundry deck for your technology. The values in this chapter are examples.

3.2  What a fill shape is, and what it costs

Figure 4 compares the two, with an idealized equivalent circuit under each.

Wires, floating fill and connected fill

Top view of a fill shape between two wires, with an idealized equivalent circuit below each panel

What to notice: Cwf is net A to fill, and Cfb is fill to net B. Real extraction reduces many coupled conductors, so these circuits only show the idea.

Both kinds add capacitance. Floating fill adds it in a way that depends on where the other conductors are. That is why a fill tool and an extraction tool must agree on the geometry. Connected fill adds a more predictable capacitance, but it uses wiring resources to reach its rail. Most signoff fill is floating, but your technology's rule deck decides. Table 3 lists what fill costs.

3.3  Three different things called "fill"

3.4  What the fill does to one net

So C after = 28.0 + (6.0 - 0.4) + 3.6 = 37.2 fF.

The change is ΔC = 3.6 - 0.4 = +3.2 fF, which is +3.2 / 34.0 = +9.4%.

This is a sensitivity estimate, not an exact split of timing-analysis delay. It does not show that every net gains 9%, or that a coupling change always slows a path. It becomes large when it adds to the same change on every other net of the path, as the measurement section shows.

4  Density rules and fill configuration

Fill has a target to hit and zones to avoid. The target is a density rule, and the zones are keepouts. Configure both before the first run. A fill run can take a long time, and a wrong rule wastes it.

4.1  What density is, exactly

The checker slides the window across the layer, and every position must stay between the minimum and the maximum.

In this chapter the invented rule for M3 is: window 100 x 100 µm, step 50 µm, minimum 20%, maximum 70%. The checked region is the 1000 x 1000 µm core, and the windows lie fully inside it. These are examples. The foundry deck of your technology holds the real values, including how it treats the region boundary.

4.2  Worked example: where is the layer too empty?

Let us consider a strip of five overlapping windows along x, from 200 to 500 µm. The windows are 100 µm wide, so each overlaps its neighbor by half. A window has an area of 100 x 100 = 10 000 µm². Cut the strip into six tiles 50 µm wide. Table 4 gives the routed M3 metal in each tile.

The mean of the five is (14.4 + 31.0 + 55.5 + 41.2 + 18.9) / 5 = 161.0 / 5 = 32.2%. That mean is above 20%, so a check on the average would pass. The rule is on every window, and W1 and W5 both fail it. Figure 5 draws the same numbers.

Local windows against the average

Density of each window, with the rule limits and the mean

What to notice: The mean sits well above the minimum, yet W1 and W5 are below it. The rule is checked per window, not on the mean.

The windows overlap, so fill placed in T2 helps both W1 and W2.

4.3  Where fill must stay away

Figure 6 shows the kinds side by side.

The zones where fill must stay out

Plan view of one region with several layers overlaid: a macro, a clock net, a critical net, a blockage and the die edge

What to notice: Ordinary fill-to-wire spacing is the smallest, and the trim around n_4412 is wider. The clock keepout is wider still, and the macro and die edge have their own margins.

The ordinary fill-to-wire spacing of the rule is the smallest, 0.3 µm in this example. A trim around a critical net is wider than that rule. Its width is set in multiples of the layer pitch, as the configuration below shows. The 1.2 µm clock band in the figure is an example project keepout. It is separate from the -⁠clock trim, which clears fill at the -⁠trim_effort distance.

4.4  Configure the fill

innovus> restoreDesign fin_F1_cells.enc.dat stream_acc ;# load F1
innovus> source site_setup.tcl ;# replay the site setup

innovus> set_metal_fill_signoff_mode -rule_file fill/fill_rules.rul \
    -layer_map_file fill/streamOut.map \
    -fill_layer {M2 M3 M4 M5 M6} \
    -min_density {20 {M2 M3 M4 M5 M6}} \
    -window_size 100 -window_step 50 \
    -trim_effort med -clock ;# rules, layers, windows and trim for the fill engine
innovus> get_metal_fill_signoff_mode ;# read every setting back

What each option does:

• -⁠rule_file names the fill rule file for the signoff engine. The alternative is -⁠technology, which names the technology so the engine finds its rule file. Use one of them.
• -⁠layer_map_file is the stream-out layer map. The fill engine writes shapes with layer numbers, and the map relates those numbers to your layer names. A map with a missing fill datatype is the most common reason for fill that exists but is not seen later.
• -⁠fill_layer limits the layers to fill. Listing them makes the run explicit.
• -⁠min_density has the form percent layer_list. It sets the window density the trim protects. The trim uses it to avoid removing fill where that could cause a density violation. The window size and step control how it is measured.
• -⁠window_size and -⁠window_step are the window and step used when trimming looks at density. The defaults are 100 and 50, the same as the example rule. Setting them explicitly makes them visible in the readback.
• -⁠trim_effort med sets the clearance of the trim around critical nets. low is one layer pitch, med is 1.5 pitches and high is two pitches.
• -⁠clock asks the trim to keep fill away from all clock nets.

This example has an M3 pitch of 0.4 µm. So low is 0.4 µm, med is 0.6 µm and high is 0.8 µm. -⁠trim_effort and -⁠spacing cannot be used together.

It is not settled what the tool does when a requested clearance and -⁠min_density conflict. So treat the minimum as an input to the trim. Always confirm the result with an independent density check, as the repair section does.

5  Insert and inspect the fill

This step changes the metal layers. It can take a long time and produce a very large database. Inspect it before you save and measure. That keeps a defective fill from becoming the parent of everything that follows.

innovus> verifyMetalDensity -report F1_density.rpt -detailed ;# per-window density of F1

Layer   Windows checked   Below minimum   Above maximum
M2      361               31              0
M3      361               47              0
M4      361               38              0
M5      361               12              0
M6      361                6              0
Total below minimum       134

Under this example's checked region and window placement, each layer has (1000 - 100) / 50 + 1 = 19 positions along each axis. So it has 19 x 19 = 361 windows. A report that lists another count is a reason to investigate.

If the count differs, the rule, the region, the boundary handling or the layer set may differ from what you meant.

The total is 31 + 47 + 38 + 12 + 6 = 134. W1 of the worked example is one of the 47 on M3.

innovus> add_metal_fill_signoff -fill ;# run the signoff fill engine

-⁠fill is one primary action of this command, and you choose one per call. The others used in this chapter are -⁠view_fills, -⁠flatten, -⁠delete_flatten_fills, -⁠trim and -⁠delete_fill.

For a long run, -⁠bg computes the fill in the background without holding the license. Every add_metal_fill_signoff action you want to run in the background must carry -⁠bg. The run stores the fill as the HMF database. It does not make the shapes editable in the session, which keeps a session with millions of shapes responsive.

Fill generation complete.
Layers filled: M2 M3 M4 M5 M6
M3   shapes added 41204   fill area 82408 µm²
HMF database written next to the design.

5.1  Look at the fill, then measure it

innovus> add_metal_fill_signoff -view_fills ;# show the HMF fill, read only

A picture is for finding problems. It is not evidence that a rule passes, because a picture has no per-window numbers.

Timing does not use the flattened copy. It reads the fill through the extraction setting in "Extract and measure the filled design".

Figure 7 shows where the signoff fill lives and how each command reaches it. Keep it in view for the rest of the chapter.

Where the signoff fill lives

The HMF database beside the design, and the commands that read or copy it

What to notice: The flattened copy is temporary: it exists only between -flatten and -delete_flatten_fills, and the checkpoint carries the HMF database alone.

innovus> add_metal_fill_signoff -flatten ;# copy the HMF fill into the design database

innovus> verifyMetalDensity -report F2_density.rpt -detailed ;# per-window density of F2

Layer   Windows checked   Below minimum   Above maximum
M2      361               0               0
M3      361               0               0
M4      361               0               0
M5      361               0               0
M6      361               0               0

innovus> add_metal_fill_signoff -delete_flatten_fills ;# drop the copy, keep the HMF

-⁠delete_flatten_fills removes the flattened shapes without updating the HMF database. Run it when the native checks are done, so the checkpoint carries one representation of the fill. It is not settled whether a flattened copy would be written into the checkpoint, so avoid the question.

W1 now holds 1 444 + 1 156 = 2 600 µm² in 10 000, which is 26.0%. It was 14.4%.

innovus> saveDesign fin_F2_fill.enc ;# checkpoint F2, with its HMF database

saveDesign stores the design with its HMF under fin_F2_fill.enc.dat, and restoreDesign restores a design that is aware of the HMF. F2 is a new layout, and none of the reports of F0 or F1 describes it.

It is not yet accepted.

6  Extract and measure the filled design

Every timing number in the F0 reports describes a layout without fill. The F2 database holds fill, but nothing has yet looked at the capacitance it adds. Until a new extraction reads the fill, a timing report of F2 describes F1. So measure again, in a way that tells you which change caused which difference.

6.1  Which extraction can see the fill

So the plan uses the signoff effort level with -⁠pvs_fill true. The cost is a Quantus license and a run that takes longer than the native one. If you cannot run Quantus, the native -⁠assumeMetFill is a labeled alternative, and its numbers are an estimate.

6.2  Why the baseline needs to be measured again

Two things change at once. The routed handoff timed C2 with the native engine. The finishing flow times F2 with a different engine, and with the fill. If P1 gets worse, you could not tell which change did it.

The fix is a controlled baseline. Extract F1, which has no fill, with exactly the settings you will use for F2. Call that measurement F1x. The difference between F1x and F2 is then the fill and its reading. The cells, the routing and every other setting stay the same. F1x is the same layout as F1. It is a measurement condition, not a candidate. Figure 8 lays out the three measurements.

A controlled baseline separates two changes

Three measurements of P1, each with its layout and its extraction

What to notice: Only the second step isolates the fill. The first step is a baseline shift that cannot be split without a third measurement.

innovus> restoreDesign fin_F1_cells.enc.dat stream_acc ;# load F1
innovus> source site_setup.tcl ;# replay the site setup

innovus> setExtractRCMode -engine postRoute -effortLevel signoff \
    -qrcCmdFile qrc/finish.cmd -coupled true -pvs_fill false ;# signoff engine, no fill
innovus> getExtractRCMode ;# read the extraction settings back
innovus> extractRC ;# extract F1 with the finishing setup

innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_F1x -prefix F1x ;# setup timing of F1x
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_F1x -prefix F1x ;# hold timing of F1x

innovus> restoreDesign fin_F2_fill.enc.dat stream_acc ;# load F2 with its HMF
innovus> source site_setup.tcl ;# replay the site setup

innovus> setExtractRCMode -engine postRoute -effortLevel signoff \
    -qrcCmdFile qrc/finish.cmd -coupled true -pvs_fill true \
    -signoff_stream_layer_map fill/fill_extract.map ;# same setup, fill read
innovus> getExtractRCMode -pvs_fill ;# must read true
innovus> extractRC ;# extract F2 with the fill

The map file converts the stream layer and datatype numbers of the fill into Quantus layers, one line per fill layer. Without it, -⁠pvs_fill true is not valid. A missing or wrong line means that layer's fill is not extracted, and no timing error tells you.

innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_F2 -prefix F2 ;# setup timing of F2
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_F2 -prefix F2 ;# hold timing of F2
innovus> report_constraint -drv_violation_type {max_transition max_capacitance} \
    -all_violators > F2_electrical.rpt ;# transition and capacitance violators
innovus> report_analysis_coverage -verbose {violated untested} -sort reason \
    > F2_coverage.rpt ;# met, violated and untested checks

6.3  What changed

Hold moves the other way. The fill slows the data wires, so the hold slack grows from +0.021 to +0.027. Do not assume that; read it. Wires on a clock net would behave differently, and the clock net has a keepout.

The 18 and 12 untested checks are the same ones as in the routed handoff.

6.4  Where P1 lost 0.015 ns

innovus> report_timing -late -from u_acc/acc_reg_12/CK -to u_out/res_reg_3/D \
    -format {hpin net cell load slew delay arrival} > F2_P1_detail.rpt ;# P1 in detail
innovus> report_net -net n_4412 > F2_n_4412.rpt ;# wire and total capacitance of one net

The three net rows are sensitivity estimates, the same kind as for n_4412 earlier. The slew carry is not measured on its own. It is what is left of the 15.0 ps after the three estimates, and the path report shows it as slower transitions. Treat it as a residual.

P1's arrival moves from 3.014 ns to 3.029 ns against a required time of 3.020 ns. That is the -0.009 ns slack. Both times exceed the 2.5 ns period because, in this invented example, they include clock network latency.

7  Repair without breaking density

F2 fails setup by 0.009 ns. The cause is capacitance from fill that the design has no reason to keep close to P1. You want the smallest change that restores the slack, with the density rule intact. The smallest change is local, so it must be aimed.

7.1  What could be wrong, and how to tell

So the loss from F1x to F2 comes from fill capacitance, and fill capacitance is what the repair targets.

7.2  A rejected experiment: delete the fill near the path

The tempting move is to remove all fill near the path. You would use add_metal_fill_signoff -⁠delete_fill with a -⁠delete_area over the region.

As an experiment from F2 in a fresh session, P1 returns to +0.006 ns, the F1x value. But the cleared area includes W1. W1 falls back to its routed density of 14.4%. The native density check finds six M3 windows below the minimum. The verdict is in Table 9.

X1 is saved as fin_X1_rejected.enc for the record. It is not a parent, and F3 starts again from F2.

7.3  Trim only around the nets that matter

innovus> restoreDesign fin_F2_fill.enc.dat stream_acc ;# load F2 with its HMF
innovus> source site_setup.tcl ;# replay the site setup
innovus> get_metal_fill_signoff_mode ;# the fill settings must be back

innovus> add_metal_fill_signoff -trim \
    -net {n_4412 n_4417 n_4420} \
    -trim_layer {M2 M3 M4} -trim_effort med ;# clear fill around three nets

• -⁠net names the critical nets that the trim keeps clear of fill. Name only the nets whose timing needs it, because a longer list removes more fill.
• -⁠trim_layer limits the trim to the layers that matter. The nets are on M3, and the layers above and below couple to them. So M2 and M4 are included, and M5 and M6 are not.
• -⁠trim_effort sets the clearance as a multiple of the layer pitch: low is one pitch, med is 1.5 and high is two. It cannot be combined with -⁠spacing, which you use when you need an exact distance from a rule.

The timing-aware variant is -⁠slack_threshold. It trims around every net whose slack is below a value. That is wider than a named list, so it is the wrong tool when only three nets are known.

This option combination has no known worked example, so read the run log.

7.4  What each clearance costs

Pick the clearance by measuring. Make three runs from F2, one per effort level. Follow each with a new extraction and an independent density check.

The high option wins on timing and loses on density, so it is rejected. Figure 9 shows the trade-off.

The trade-off between timing and density

Left: the three trim clearances around a net. Right: P1 slack and W1 density for each option

What to notice: Only med clears both limits: P1 slack at or above 0.000 ns and W1 density at or above 20%.

W1 is the window that limits the choice. Its density after fill is (1 444 + 1 156) / 10 000 = 26.0%. After each trim it is (2 600 - removed) / 10 000: 24.5%, 22.7% and 19.0%. The last is below the 20% minimum.

The configuration passed a minimum of 20% to the engine. Still, in this invented run the independent check found W1 at 19.0%. It is not settled whether the tool stops short of the clearance or only warns in that case. That is why the density check after the trim is part of the procedure, not an extra.

7.5  Re-extract, re-measure, save

innovus> setExtractRCMode -engine postRoute -effortLevel signoff \
    -qrcCmdFile qrc/finish.cmd -coupled true -pvs_fill true \
    -signoff_stream_layer_map fill/fill_extract.map ;# same setup as for F2
innovus> getExtractRCMode -pvs_fill ;# must read true
innovus> extractRC ;# extract the trimmed layout
innovus> timeDesign -postRoute -expandedViews -numPaths 200 \
    -outDir timing_F3 -prefix F3 ;# setup timing of F3
innovus> timeDesign -postRoute -hold -expandedViews -numPaths 200 \
    -outDir timing_F3 -prefix F3 ;# hold timing of F3
innovus> report_constraint -drv_violation_type {max_transition max_capacitance} \
    -all_violators > F3_electrical.rpt ;# transition and capacitance violators
innovus> report_analysis_coverage -verbose {violated untested} -sort reason \
    > F3_coverage.rpt ;# met, violated and untested checks

innovus> add_metal_fill_signoff -flatten ;# bring the fill in for the density check
innovus> verifyMetalDensity -report F3_density.rpt -detailed ;# per-window density
innovus> add_metal_fill_signoff -delete_flatten_fills ;# drop the flattened copy

innovus> saveDesign fin_F3_repair.enc ;# checkpoint F3

After the trim, the delay added on P1's nets is 0.8 + 0.6 + 0.8 ps, plus 0.8 ps of slew residual. That is 3.0 ps in total, against 15.0 ps in F2. The trim recovered 12.0 ps. Check: -0.009 + 0.012 = +0.003.

Coverage for F3 is 4 002 + 0 + 18 = 4 020 for setup. For hold it is 4 008 + 0 + 12 = 4 020. The 18 and 12 untested checks are the same as before. Figure 10 puts the four measurements side by side.

P1 slack in four measurements

Left: P1 setup slack against the stage target. Right: the delay added on P1, by cause

What to notice: The trim gives back 12.0 ps. The final slack of +0.003 ns is positive but thin.

8  Verify the finished candidate

F3 is the candidate you intend to hand off. Before it leaves, ask what is true of exactly this layout, one question at a time. Different checks answer different questions, and a pass on one tells you nothing about another. The commonest finishing mistake is to read one clean report as "the layout is fine". Examples are a clean connectivity report or a green density map.

8.1  Six questions, kept separate

Each check may pass while the layout still fails a question that check does not ask.

8.2  Check the scope before you read the result

A density report has a built-in plausibility test. Under this example's checked region and window placement, each layer reports 361 windows. A different count does not prove the run is bad. It tells you to look at the rule, the region and the layer set before you trust the result. The three traps and the test are summed up in Figure 11.

Three ways a check looks at less than you think

Read the scope before you read the result

What to notice: Each trap has its own readback: the rule-check mode, the fill-wire setting, and whether you flattened.

8.3  Run the checks on F3

innovus> restoreDesign fin_F3_repair.enc.dat stream_acc ;# load F3 with its HMF
innovus> source site_setup.tcl ;# replay the site setup
innovus> get_metal_fill_signoff_mode ;# confirm the fill settings came back

innovus> set_verify_drc_mode -ignore_fill_wire false -limit 1000 ;# include fill wires
innovus> get_verify_drc_mode ;# read the scope back

innovus> add_metal_fill_signoff -flatten ;# copy the HMF fill into the database

innovus> verifyConnectivity -type all -error 50 -warning 50 ;# opens and unrouted nets
innovus> verify_drc -report F3_drc.rpt ;# rule check, fill included
innovus> verifyMetalDensity -report F3_density.rpt -detailed ;# per-window density
innovus> verify_antenna -report F3_antenna.rpt ;# antenna check

innovus> checkFiller -file F3_filler_gaps.rpt ;# gaps left
innovus> verifyEndCap -report F3_endcap.rpt ;# end caps
innovus> verifyWellTap -report F3_welltap.rpt ;# well taps

innovus> add_metal_fill_signoff -delete_flatten_fills ;# keep only the HMF fill

verifyConnectivity   Open 0   Unrouted 0
verify_drc           Total 0
verifyMetalDensity   M2..M6: 361 windows each, 0 below, 0 above
verify_antenna       Total 0
checkFiller          Total number of gaps found: 0
verifyEndCap         Violations 0
verifyWellTap        Violations 0

8.4  Which report belongs to which layout

A file's age is a warning sign, not a test. Saving an unchanged layout does not make its reports stale, and a copied file gets a new time. The deciding record is provenance: which checkpoint, which session, which settings, all in the manifest.

Table 13 lists the checks by what each run actually covered. "Run" means a run exists on that layout. Only the F3 column supports the F3 handoff, and every other cell describes an earlier layout.

Figure 12 draws the facts of Table 13 on the lineage of the candidates.

Candidates, a measurement, a rejected experiment and their reports

The lineage C2 to F3, with one report chip per check under each candidate

What to notice: F3 descends from F2, not from X1. Only the filled chips under F3 support the handoff; antenna ran on F3 alone.

9  Export and hand off

The receiving team will never see your session. It sees files and a record. Whatever the files do not carry does not exist for them. Examples are a layer that was not mapped and a cell that was not merged. So export from the exact candidate you verified, check what you wrote, and write a record. The record says which checks ran, which did not, and who owns the rest.

9.1  What stream-out needs before it runs

Some installations spell the fill option -⁠signoff_fill and others -⁠pvs_fill. Run streamOut -⁠help and use the spelling it prints. The block below uses -⁠signoff_fill.

innovus> restoreDesign fin_F3_repair.enc.dat stream_acc ;# load F3 with its HMF
innovus> source site_setup.tcl ;# replay the site setup
innovus> get_metal_fill_signoff_mode ;# confirm the fill settings came back

innovus> streamOut stream_acc_F3.gds -mapFile fill/streamOut.map \
    -libName DesignLib -structureName stream_acc -units 1000 \
    -mode ALL -signoff_fill \
    -merge {gds/u_buf_a.gds gds/u_buf_b.gds gds/u_coef.gds \
    gds/stdcells.gds} \
    -reportFile stream_acc_F3_streamout.rpt ;# write the GDSII of F3 with its fill

Export from a restored F3, not from the session where you ran the density check or the trial trims. A session that has run experiments may hold a flattened copy, an edited setting or a different candidate.

Figure 13 shows the whole export: inputs, the files written, and the three levels of checking that follow.

What leaves the session, and how you check it

The restored F3 feeds stream-out and the other writers; three checks of increasing strength follow

What to notice: Each validation level proves more than the one before it. Only the receiving side's readback compares the file against the manifest.

9.2  What else the receiving team needs

innovus> saveNetlist stream_acc_F3.v ;# logical netlist
innovus> saveNetlist stream_acc_F3_phys.v -includePhysicalInst \
    -includePowerGround ;# netlist with physical instances and power
innovus> defOut -routing stream_acc_F3.def ;# routed wires as DEF

9.3  Validate what you wrote

innovus> file size stream_acc_F3.gds ;# Tcl file size in bytes
innovus> exec md5sum stream_acc_F3.gds ;# shell checksum for the manifest

Both commands above run at the Innovus prompt but are not Innovus commands. file size is plain Tcl, and exec md5sum calls the Linux shell.

9.4  The handoff record

Figure 14 shows the split between the two decisions on the record of F3.

Handoff readiness against signoff readiness

The fifteen rows of the record, split by who owns each check

What to notice: NOT RUN is written as words, never as a 0, and it never counts as a pass.

A check has three outcomes, not two: it passed, it failed, or it did not run. A table with a 0 for a check that never ran reads as "no violations". It really means "nobody looked".

So the record uses words in the status column, and a number only where a tool produced it. A check that belongs to the receiving team is recorded as NOT RUN with its owner. That is a pending responsibility, not an exception to the producer's handoff. It is never counted as a pass. The record for F3 is in Table 18 and Table 19.

Rows 1 to 10 ran on F3 and are tied to its checkpoint in the manifest. Rows 11 to 15 have no file.

9.5  The exceptions

The stage target of 0.000 ns is an invented value of the example. The receiving project's number is the one that counts.

9.6  Decision

F3 is ready for handoff with documented exceptions E1 and E2. It is not signoff-ready, and this record does not claim that. Rows 11 to 14 are pending with the receiving team, and row 15 is outside this chapter.

Anything that edits the layout, even one wire or one fill shape, makes F3 a new candidate. It returns you to "Extract and measure the filled design". The lineage is C2, F0, F1, F2, F3. F1x is a measurement of F1, and X1 is a rejected experiment that parents nothing. The handoff note carries the items in Table 21.

10  Debug index and open caveats

Finishing failures are expensive to guess at, because each rerun of fill or extraction takes a long time. The sections above carry the detail. This section is the index: find the symptom, run the first check, and go to the section that repairs it.

Use the same order every time. Start from the symptom and its evidence, then list the competing causes. Run a check that tells them apart, make a scoped repair, and measure the repaired candidate again.

10.1  Open caveats to settle in your installation

These points are not settled for every release. Note them before you rely on a result.

• The fill option of streamOut is spelled -⁠signoff_fill in some installations and -⁠pvs_fill in others. Use the spelling that -⁠help prints.
• The default of deleteFiller -⁠keepFixed is unclear, so fixed end caps and taps may or may not survive. Always pass -⁠prefix or -⁠cell to deleteFiller.
• Confirm every setMetalFill and addMetalFill option with -⁠help before you use it.
• The default of set_verify_drc_mode -⁠ignore_fill_wire is unclear. Set it, then read it back.
• It is not settled whether the native checks read HMF fill without -⁠flatten, or whether saveDesign would write a flattened copy. This chapter flattens for the checks and deletes the flattened copy afterwards.
• It is not settled what the trim does when a requested clearance and -⁠min_density conflict. This chapter verifies density independently after every trim.
• defOut has no option for signoff fill, so the fill travels only in the stream file.
• If you need the global connection rules as a script, try writeFplanScript -⁠sections {globalNetConnect}. Confirm it with -⁠help first.
• The combination -⁠trim -⁠net -⁠trim_layer -⁠trim_effort has no known worked example. Read the run log after the first trim.

10.2  Common mistakes and how to catch them

11  Interview preparation

Compact glossary

Chip finishing on one page

Where the next chapter goes, and why

F3 is handed off with a record. That record lists what is still open: signoff timing with its own extraction, and a thin +0.003 ns margin on P1.

The next chapter, Signoff Preparation and Timing ECO Closure, picks up exactly there. It prepares the signoff timing run and closes the paths that fail there with ECOs. Every ECO edits the layout, so the habits of this chapter come with you. Each edit means a new candidate name, incremental fill and a fresh extraction. The evidence is again tied to the exact layout.