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Physical Verification & ASIC Signoff Academy

Master the Complete ASIC Signoff Flow

Build practical confidence in DRC, LVS, ERC, antenna, power reliability, parasitic extraction, STA, MMMC, logical equivalence and tapeout handoff.

Explore the 13 Guides

Source verified: every title, topic and page count comes from the supplied pdVerse guide PDFs.

Forest-green 3D technical book about IR drop and electromigration
Purple 3D technical book for geometric rule checking
Copper-brown 3D technical book about timing and crosstalk
Dark teal 3D technical book about electrical rule checking
Emerald 3D technical book about low-power structural checks
Crimson 3D technical book about antenna reliability
Blue 3D technical book illustrating layout-versus-schematic comparison
13practical guides
520source-verified pages
4learning tracks
1complete signoff workflow

Complete 13-Guide Library

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One ZIP containing all 13 source-verified pdVerse signoff guides

Guide Catalogue

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Showing all 13 guides

Purple 3D technical book for geometric rule checkingDRC SIGNOFF
33 pages

DRC Signoff Mentor Guide

Prepare, run, debug and prove final design-rule closure.

  • Rule decks
  • Layer maps
  • Violation debug

What you'll learn

  • Prepare ICC2 signoff layout
  • Debug geometric markers
  • Package closure evidence

Interview Q&A

  • What is the difference between a DRC error and a DRC waiver?
  • How do you prioritize DRC violations when hundreds remain?
  • Explain the role of rule decks in signoff DRC.
Blue 3D technical book illustrating layout-versus-schematic comparisonLVS VERIFICATION
81 pages

ASIC LVS Flow with ICC2 and IC Validator

Compare extracted connectivity with source intent and isolate mismatches.

  • ICV LVS
  • Netlist extraction
  • Mismatch debug

What you'll learn

  • Prepare layout and source netlist
  • Run extraction and comparison
  • Read and debug LVS reports

Interview Q&A

  • What causes an LVS mismatch after a clean DRC run?
  • How does netlist extraction handle power and ground rails?
  • Describe your approach to debugging an open vs short in LVS.
Crimson 3D technical book about antenna reliabilityANTENNA RELIABILITY
46 pages

Understanding Antenna Violations in ICC2

Recognize plasma-charging risk and close violations inside implementation.

  • Antenna ratios
  • Aware routing
  • Diode repair

What you'll learn

  • Understand antenna physics
  • Detect routing risk
  • Repair and verify closure

Interview Q&A

  • What physical mechanism causes antenna damage during fabrication?
  • How does gate-oxide area ratio relate to antenna violations?
  • What is the difference between a diode fix and a jumper fix for antenna?
Silver and cyan 3D technical book about metal densityMETAL FILL
39 pages

Understanding Metal Fill and Density Signoff

Meet manufacturing density requirements without losing electrical confidence.

  • Density windows
  • Pattern fill
  • Post-fill impact

What you'll learn

  • Understand density requirements
  • Create and review fill
  • Close electrical impact

Interview Q&A

  • Why is metal density important for CMP uniformity?
  • How can dummy fill affect parasitic capacitance and timing?
  • What is the difference between pattern fill and non-pattern fill?
Dark teal 3D technical book about electrical rule checkingERC
45 pages

ASIC ERC Flow with ICC2, ICV, and ICV PERC

Find electrical hazards that clean geometry and connectivity cannot prove.

  • ICV PERC
  • Power domains
  • Violation triage

What you'll learn

  • Prepare electrical intent
  • Run qualified ERC checks
  • Repair and document violations

Interview Q&A

  • What electrical violations can pass DRC and LVS but fail ERC?
  • How does ICV PERC differ from standard DRC checks?
  • Give an example of a power-domain ERC violation.
Emerald 3D technical book about low-power structural checksCLP
42 pages

Understanding and Debugging ASIC CLP Checks

Validate isolation, level shifting, retention and legal power states.

  • UPF
  • Isolation
  • Retention

What you'll learn

  • Check RTL through post-route
  • Debug strategy failures
  • Validate states and waivers

Interview Q&A

  • What is the difference between isolation and level shifting?
  • How do CLP checks validate UPF power-state tables?
  • When would a retention register fail a CLP check?
Forest-green 3D technical book about IR drop and electromigrationPOWER RELIABILITY
49 pages

Power Reliability Signoff Mentor Handbook

Connect IR, EM and thermal results to physical root causes and ECOs.

  • Static & dynamic IR
  • EM
  • ICC2 ECOs

What you'll learn

  • Set up reliability analysis
  • Read visual results
  • Prove post-ECO closure

Interview Q&A

  • What is the difference between static and dynamic IR drop?
  • How does electromigration (EM) relate to wire width and current density?
  • What ECOs are typical after a failed power reliability check?
Turquoise and gold 3D technical book about chip-to-package integrityPACKAGE & I/O
28 pages

Package and I/O Signoff Mentor Guide

Trace connectivity and constraints from core logic to package balls.

  • Pad rings
  • Bump maps
  • Package handoff

What you'll learn

  • Trace the core-to-ball path
  • Validate naming and loading
  • Release a controlled handoff

Interview Q&A

  • What is the significance of pad-ring ordering in package signoff?
  • How do bump maps differ from wire-bond pad maps?
  • What naming mismatches commonly cause package handoff failures?
Burnt-orange 3D technical book about post-fill extractionPARASITIC EXTRACTION
34 pages

Post-Fill Parasitic Extraction with StarRC

Build a correlated post-fill handoff and validate extracted parasitics.

  • StarRC
  • SPEF / GPD
  • Corner validation

What you'll learn

  • Prepare the ICC2 handoff
  • Align models and layer maps
  • Sanity-check extraction output

Interview Q&A

  • What is the difference between SPEF and GPD extraction formats?
  • Why must parasitic extraction happen after metal fill?
  • How do you validate that extracted RC values are reasonable?
Copper-brown 3D technical book about timing and crosstalkSTA & SIGNAL INTEGRITY
44 pages

Static Timing Analysis and Signal Integrity

Close timing, variation and crosstalk against a trustworthy physical revision.

  • PrimeTime
  • OCV / POCV
  • Signal integrity

What you'll learn

  • Build signoff timing context
  • Analyze variation and SI
  • Package closure evidence

Interview Q&A

  • What is OCV derating and why is it needed for signoff?
  • How does crosstalk affect setup vs hold timing differently?
  • Explain the difference between GBA and PBA timing analysis.
Burgundy 3D technical book about multi-mode multi-corner validationMMMC
39 pages

MMMC Setup and Corner Validation

Build complete scenarios and correlate ICC2 with PrimeTime.

  • Modes
  • Corners
  • Correlation

What you'll learn

  • Construct analysis views
  • Validate libraries and constraints
  • Debug coverage and correlation

Interview Q&A

  • What are the components of an MMMC analysis view?
  • How do you debug a scenario where ICC2 and PrimeTime disagree?
  • Why must library sets, constraint modes, and RC corners all be validated?
Indigo 3D technical book about formal equivalence checkingLOGICAL EQUIVALENCE
28 pages

Understanding and Debugging ASIC LEC with Formality

Prove implementation changes preserve the intended logical function.

  • Formality
  • Compare points
  • ECO signoff

What you'll learn

  • Set up reference comparison
  • Interpret counterexamples
  • Debug equivalence mismatches

Interview Q&A

  • What is a non-equivalent point and how does Formality report it?
  • How do you handle scan-chain reordering in LEC?
  • When would you use HDL versus gate-level reference for LEC?
Matte-black 3D technical field guide with lime detailsTAPEOUT CHECKLIST
12 pages

ASIC Signoff Cheat Sheet

Map each signoff check to its required inputs, outputs and evidence.

  • Release manifest
  • Signoff inputs
  • Evidence package

What you'll learn

  • Track required PNR inputs
  • Review commands and outputs
  • Package the tapeout manifest

Interview Q&A

  • What does a complete signoff evidence package contain?
  • List the inputs required before running timing signoff.
  • How do you verify that no signoff check was skipped at tapeout?

A Practical Learning Path

Follow the same dependency chain used in signoff.

  1. 1

    Geometry & Manufacturability

    Prove the layout is buildable and connectivity matches intent.

  2. 2

    Electrical & Power

    Validate power intent, electrical safety and delivery strength.

  3. 3

    Timing & Correlation

    Use trusted physical data to close extraction, timing, SI and logic.

  4. 4

    Tapeout Handoff

    Bind every result to one auditable release revision.

The Disciplined Loop

Evidence before approval.

Every guide follows one repeatable closure method.

  1. 1Prove inputsConfirm revision, decks, models and intent.
  2. 2Prove completionVerify the intended stages actually ran.
  3. 3Fix root causeCorrect the right source of truth.
  4. 4Package evidenceBind reports and waivers to the release.
Reference boundary: the supplied 518-page Synopsys IC Validator User Guide is vendor documentation used to verify tool concepts and commands. It is not presented or sold as a pdVerse guide.

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