Modes Functional Scan shift Low power SS/0.9V/125C TT/1.0V/25C FF/1.1V/-40C Each cell = one analysis scenario (mode × corner) What are RC corners (Cmax/Cmin/RCmax/RCmin), and why might the worst corner differ between a short capacitance-dominated net and a long resistance-dominated net?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Technical Explanation
RC corners model interconnect extremes from process variation in wire width and spacing: Cmax (wider width, closer spacing, lower R, higher C) is setup-worst on short capacitance-dominated nets; Cmin (narrower width, farther spacing, higher R, lower C) is hold-worst on capacitance-dominated nets; RCmax (narrower width, higher R, mixed C) is setup-worst on long resistance-dominated nets; RCmin (wider width, lower R, mixed C) is hold-worst on resistance-dominated nets.
Timing-path Reasoning
Wire width and spacing variation moves resistance and capacitance in opposite directions: a wider, closer-spaced wire has lower resistance but higher capacitance, while a narrower, farther-spaced wire has higher resistance but lower capacitance. For a short net where capacitance dominates delay, the corner that maximizes capacitance (Cmax) is the setup-worst case, and the corner minimizing it (Cmin) is hold-worst. But for a long net where resistance dominates delay (due to accumulated wire resistance along its length), the corner that maximizes resistance (RCmax, from narrower width) becomes setup-worst even though capacitance behaves differently, and RCmin (wider width, lower resistance) becomes hold-worst. This means the single 'worst' RC corner is not universal — it depends on whether a given net's delay is capacitance-dominated or resistancedominated.
Expected Result
A rigorous signoff methodology checks both capacitance-dominated short nets against Cmax/Cmin and resistance-dominated long nets against RCmax/RCmin, rather than assuming one RC corner covers all net types.
Failure Symptoms
Signing off only against one assumed-worst RC corner can miss real violations on the net type for which that corner is not actually the worst case — e.g., checking only Cmax/ Cmin might miss a setup violation on a long resistance-dominated net whose true worst case is RCmax.
Root Cause
Width and spacing variation affecting R and C in opposite directions, meaning no single RC corner simultaneously maximizes or minimizes both parameters for every net topology.
Mentor Note — Debugging Procedure
For each net class in the design (short/capacitance-dominated vs long/resistancedominated), confirm the timing analysis includes checks against the RC corner that is actually worst for that net's delay-dominant parameter, rather than relying on a single assumed corner across the whole design. Don't assume a single RC corner is worst for all net types — width variation moves R and C in opposite directions, so short capacitance-dominated nets and long resistance-dominated nets can have opposite worst-case RC corners, requiring both Cmax/Cmin and RCmax/RCmin checks for complete coverage.
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