Level 3 · Signoff Reasoning

Expert STA Interview Questions

Reason through variation, CRPR, crosstalk, MCMM, ECO flows, correlation, and defensible timing signoff.

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Reason through variation, CRPR, crosstalk, MCMM, ECO flows, correlation, and defensible timing signoff.

  1. 01 Walk through a full setup check including clock reconvergence pessimism (CRPR) — why does OCV derating create artificial pessimism on shared clock paths, and how is it removed?Expert · A full setup check compares data arrival against the required time, but when launch and capture clocks share a common trunk before diverging, applying OCV derates independently to each side double-counts variation on that shared segment.
  2. 02 How does temperature inversion complicate the assumption that hold is always worst at the fast/cold corner?Expert · At low operating voltage, cell delay can actually increase as temperature drops, because the threshold voltage's temperature dependence starts to dominate over the usual mobility-driven speed-up — this is temperature inversion.
  3. 03 How do you model and verify timing across multiple clock domains with different frequencies (e.g., a 2:1 frequency crossing)?Expert · A frequency-divided clock relationship is modeled with a generated clock definition that ties the derived clock's edges to a divide ratio off the source clock, letting the tool compute the correct synchronous relationship between the two domains.
  4. 04 What goes wrong when a compound generated clock (divide-then-gate) is defined incorrectly, and how do you validate it?Expert · A compound generated clock — one that is both divided and gated from its source — must correctly encode both operations, or the tool will compute wrong edges, wrong periods, or misclassify the clock's relationship to other clocks in the design.
  5. 05 What is the exact mechanism by which clock reconvergence pessimism removal (CRPR/CPPR) computes its credit?Expert · CRPR looks at the clock tree from its root down to the point where the launch and capture paths diverge, computes how much the early and late derated delays differ across that shared segment, and adds that difference back into the timing slack as a credit.
  6. 06 What is on-chip variation (OCV), and how is it different from PVT corner variation?Expert · OCV is the phenomenon that identical devices in different locations on the same die behave slightly differently, due to random dopant fluctuation, lithography variation, systematic gradients, and local temperature or voltage differences — distinct from the global variation captured by PVT corners.
  7. 07 How does AOCV (path-depth/distance-dependent derating) reduce pessimism compared to flat OCV , with a worked numeric example?Expert · AOCV makes the derate factor depend on path characteristics — chiefly path depth (number of stages) and sometimes distance — instead of applying one flat derate everywhere, because statistically, variation partially cancels out over many stages rather than accumulating at the same rate as a single-stage flat multiplier would suggest.
  8. 08 How does POCV combine per-arc sigma values, and how does that scale differently than flat derating as path length grows?Expert · POCV models variation statistically per timing arc rather than with derate factors: each arc carries a nominal delay and a standard deviation (sigma) from the library's variation data, and these sigmas are combined along a path in a root-sum-square (RSS) statistical sense rather than added linearly.
  9. 09 What command applies OCV/AOCV derating, and how do -early/-late and cell_delay/-net_delay/-clock/-data qualifiers change what gets derated?Expert · set_timing_derate is the command that applies OCV derate factors, with qualifiers letting you target exactly which delay components (cell vs net, clock vs data) get derated and in which direction (early/late).
  10. 10 What is the exact mechanism by which crosstalk delay differs from crosstalk noise, and why does the Miller effect make an opposite-switching aggressor roughly twice as impactful as a quiet one?Expert · Crosstalk delay happens when the victim net is itself switching and the aggressor's injected current adds to or subtracts from the victim's own transition, shifting when the victim edge crosses its switching threshold; crosstalk noise (a glitch) happens when the victim is quiet and the injected current produces a spurious bump instead.
  11. 11 Why can summing every aggressor's worst-case crosstalk contribution be overly pessimistic, and what actually limits how many aggressors can realistically align?Expert · Summing individual aggressors' worst-case contributions is pessimistic because it assumes every aggressor can switch at exactly the moment needed to maximally disturb the victim, but each aggressor's own timing window — the range of times its edge can actually occur given its own paths and clock relationships — may not overlap the victim's edge at all.
  12. 12 Does PrimeTime (per the supplied PTUG) provide a command to create or schedule 'useful skew,' or is that a different tool's job — and what does PrimeTime actually give you regarding skew?Expert · Based on the sampled PTUG material, PrimeTime does not include a command to create or schedule useful skew — that is implemented upstream in synthesis/CTS tools. PrimeTime's role is analysis and reporting of skew, not skew synthesis.
  13. 13 What is the difference between set_false_path/set_max_delay and the more surgical set_disable_timing, and how does exception precedence resolve conflicts between them?Expert · set_false_path and set_max_delay define exceptions on a specific point-to-point path basis, while set_disable_timing removes timing arcs through a given pin entirely, which is more efficient when every path through that pin is genuinely false.
  14. 14 What options does PrimeTime provide for filtering and reporting specific timing paths (through/from/to, nworst, path tagging), and why would you use path tagging for exhaustive PBA?Expert · report_timing offers extensive filtering to scope exactly which paths get reported — including multiple -through lists, -input_pins, -max_paths N, -slack_lesser_than, and path-based analysis mode selection — while path tagging lets you mark alreadyanalyzed paths so successive exhaustive PBA runs don't redundantly re-analyze them.
  15. 15 What is the difference between 'union' and 'every-group' TNS computation in report_global_timing, and why does this matter for DMSA (multi-scenario) results?Expert · The timing_report_union_tns variable controls whether Total Negative Slack is computed as a 'union' (true, the default) across overlapping violation categories or as 'every- group' (false), summing each group's violations separately, which changes the reported TNS magnitude especially when combining results across DMSA scenarios.
  16. 16 Walk through the fix_eco_timing flow for setup versus hold, and explain why the recommended ECO fixing order matters.Expert · fix_eco_timing -type setup fixes setup violations using cell sizing only, with no buffer insertion or clock-network changes by default, while fix_eco_timing -type hold uses both cell sizing and buffer insertion, and the overall ECO order matters because each fixing step can create or interact with violations the next step must respect.
  17. 17 What is MCMM/DMSA (multi-mode multi-corner / distributed multiscenario analysis), and what commands does PrimeTime provide to manage it?Expert · MCMM is verifying and optimizing timing across the cross-product of functional modes and analysis (PVT) corners, with each mode-corner combination forming a scenario; DMSA is the distributed execution architecture where a master PrimeTime session coordinates per-scenario worker sessions and merges their results.
  18. 18 Modes Functional Scan shift Low power SS/0.9V/125C TT/1.0V/25C FF/1.1V/-40C Each cell = one analysis scenario (mode × corner) What are RC corners (Cmax/Cmin/RCmax/RCmin), and why might the worst corner differ between a short capacitance-dominated net and a long resistance-dominated net?Expert · RC corners model interconnect extremes from process variation in wire width and spacing: Cmax (wider width, closer spacing, lower R, higher C) is setup-worst on short capacitance-dominated nets; Cmin (narrower width, farther spacing, higher R, lower C) is hold-worst on capacitance-dominated nets; RCmax (narrower width, higher R, mixed C) is setup-worst on long resistance-dominated nets; RCmin (wider width, lower R, mixed C) is hold-worst on resistance-dominated nets.
  19. 19 What does a rigorous 'timing is clean' signoff declaration actually require, beyond a report showing zero violations?Expert · A trustworthy signoff requires working through a full checklist of analysis dimensions — corners, OCV/derating, crosstalk, MCMM scenarios, exceptions — and confirming each is genuinely covered, because any unchecked box represents a silent risk that a green, zero-violation report will not reveal on its own.
  20. 20 An engineer says 'silicon always beats signoff, so our margins must be too conservative.' How do you respond, and what's the danger in that reasoning?Expert · Observing that real silicon consistently outperforms signoff timing might indicate recoverable over-pessimism worth investigating, but it can also be a dangerous overgeneralization masking real risk, because typical-part correlation samples used for that observation don't include the tail or worst-process parts that signoff margins actually exist to protect.