STA Interview Questions and Answers

STA is a method for checking that a synchronous digital chip meets its timing requirements without actually simulating it with input vectors.

Simulation only checks the specific input patterns (vectors) you feed it, while STA statically examines every timing path in the design regardless of what vectors you would have…

A timing path is the route a signal takes from a startpoint, through combinational logic, to an endpoint.

Startpoints are where a path begins — input ports and clock pins of sequential elements; endpoints are where it ends — output ports and the data-input pins of sequential elements.

These four categories describe where a path begins and ends: reg2reg (flip-flop to flipflop), in2reg (input port to flip-flop), reg2out (flip-flop to output port), and in2out…

You define a clock using SDC (Synopsys Design Constraints), the industry-standard Tclbased format for describing a design's timing intent, and the create_clock command is what…

Data arrival time is when a signal actually reaches a given node, computed by adding up all the delays along the path leading to it.

Data required time is the latest moment (for a setup check) or earliest moment (for a hold check) that a signal is allowed to arrive at its destination.

A setup check verifies that data launched by one clock edge arrives at the capturing flipflop's D pin early enough — specifically, at least a setup time (Tsu) before the…

A hold check verifies that data launched by a clock edge does not arrive at the capturing flop too soon after that same edge — the data must stay stable until a hold time (Th)…

Slack is the margin by which a timing check passes or fails — the difference between the required time and the arrival time.

Positive slack means a path has margin to spare and passes its timing check; negative slack means the path violates its check and fails.

The launch flip-flop is the one that sends data out on a clock edge (the launch edge), and the capture flip-flop is the one that captures that data on a later clock edge (the…

set_input_delay models how long after a clock edge the data actually arrives at an input port, telling the STA tool how much of the clock period is already used up before the…

set_output_delay models how much time before the external clock edge the data must leave an output port, capturing the timing budget consumed by whatever sits outside the chip…

Clock uncertainty is a margin subtracted from the available timing budget to account for imperfections in the clock, chiefly jitter, plus any additional margin or guardband the…

Clock latency, also called insertion delay, is the absolute time it takes the clock to travel from its source to a flip-flop's clock pin; it splits into source latency, the delay…

Clock skew is the difference in clock arrival time between two points — specifically, capture arrival time minus launch arrival time.

Combinational (logic) delay is the portion of a timing path's delay that comes from the chain of logic gates and interconnect between the launch point and the capture point, as…

Cell (gate) delay is the time from when an input of a logic cell crosses its switching threshold to when the output crosses its threshold — essentially the internal switching…

Net delay is the time a signal takes to travel along a wire from one cell's output pin to the next cell's input pin, after the driving cell has already produced its output.

A report_timing output walks the path hop by hop from the startpoint flop to the endpoint flop, showing an incremental delay (Incr) and a running total (Path) at each point, then…

SDC stands for Synopsys Design Constraints, and it is the industry-standard Tcl-based text format used to write down a design's timing intent for the STA tool to read.

A setup check makes sure data arrives at a flop's input early enough, before the capturing clock edge, with some margin to spare. A setup violation means slack is negative, so…

Slack, in general, is required minus arrival, and a violation of any kind (setup or hold) simply means that slack has gone negative for that check.

Slew, also called transition time, is the amount of time it takes a signal's waveform to swing between two defined threshold points, commonly the 20 percent and 80 percent levels.

A standard-cell library holds the characterized timing (and power) data for every logic cell used in the design, and Liberty (.lib) is the structured, text-based format used to…

NLDM stands for Non-Linear Delay Model. It represents a cell's timing arc delay (and output transition) as a two-dimensional lookup table, indexed by the input slew coming into…

PVT corners refer to combinations of Process, Voltage, and Temperature conditions at which a standard cell's timing is characterized. A library is not one single file, it ships…

An ideal clock is modeled as reaching every flop instantly, or with just a fixed, uniform latency number, before any real clock tree/network has even been built. A propagated…

WNS, or Worst Negative Slack, is simply the single most negative slack value found anywhere in the design among all the violating (failing) paths.

TNS, or Total Negative Slack, is the sum of all the negative slack values across every violating path in the design, not just the worst one.

A generated clock is a clock signal that is derived from a master clock (or from another already-generated clock) by some on-chip logic, such as a divider, a clock gate, a…

A false path is a path through the netlist that STA is able to trace topologically (structurally, following the logic connections) but that can never actually be exercised during…

A multicycle path is a path where the design's intended behavior allows the data more than a single clock cycle to travel from its launching flop to its capturing flop, rather…

check_timing is a constraint sanity check: it scans the design and SDC setup for problems like endpoints that were never constrained, flops that have no clock reaching them,…

Parasitics are unintended electrical properties, resistance and capacitance, that physically exist in interconnect (metal wires and vias) simply because those wires are made of…

Pre-layout STA runs before physical placement and routing exist, so it relies on estimated or wire-load-based parasitics as a stand-in for real wires. Post-layout (postroute) STA…

A standard timing run is fed by several key inputs together: the netlist (the actual gatelevel logic connections), the timing library (characterized cell delay/timing data, in…

Timing signoff is the formal declaration that a design meets all of its timing requirements under the agreed-upon conditions, and is therefore considered safe to tape out (send…

A setup check makes sure data launched by one clock edge arrives at the capture flop with enough margin before the next active edge. The tool adds up everything that delays the…

A hold check guards against data racing through too fast and corrupting the previous value still needed at the capture flop. It compares the fastest possible data arrival (using…

Before layout, STA typically assumes an idealized clock (arriving everywhere at the same time, zero skew). set_propagated_clock switches the tool to compute the clock's actual…

Hold checks depend heavily on skew (S) between launch and capture clock arrival. If the clock is still treated as ideal after the real tree is built, every flop appears to…

Clock jitter is the clock edge itself wobbling cycle to cycle at its source — an inherent property of the clock generator. Clock uncertainty is a margin the timing tool is told…

Source latency models the delay from the clock's true origin (such as an off-chip source or a PLL) to the point where the clock is defined in the design. Network latency models…

A DDR (double data rate) interface can launch or capture data on both clock edges, so a single input delay referencing only the rising edge isn't enough. -clock_fall tells the…

A false path is a path that STA can trace through the netlist topologically but that the engineer asserts can never actually be exercised in functional operation — for example, a…

set_multicycle_path relaxes the setup check to allow data more than one clock cycle to arrive, but it does not automatically move the hold check's reference edge. Without an…

set_clock_groups classifies relationships between clock domains for timing (and sometimes crosstalk) purposes. -asynchronous marks clocks with no fixed phase relationship, so…

A generated clock is one derived from a master (or another generated) clock by on-chip logic — a divider, clock gate, multiplexer, or inversion. It must be defined with…

Recovery and removal checks apply to asynchronous control signals like reset, verifying they're properly synchronized relative to the clock even though they aren't clocked data.…

max_transition is a design-rule ceiling on the largest transition (slew/edge rate) time a cell input or output pin is allowed to see, independent of whether the path otherwise…

max_capacitance is a design-rule ceiling in the standard cell library specifying the largest output load (capacitance) a cell or pin is allowed to drive, listed as a pin-group…

When multiple timing exceptions could apply to the same path, the tool resolves them by precedence rather than combining them — and false path exceptions take precedence over…

GBA keeps a single worst-case slew at each node in the timing graph and reuses that same value for every path passing through it — fast to compute, but pessimistic, since it can…

report_timing prints a Point/Incr/Path table walking down the launch path arc by arc, showing each cell or net's incremental delay and the running cumulative total. To find the…

check_timing scans the design for constraint problems that would make timing analysis incomplete or wrong — things like flops with no clock, ports with no output or input delay,…

group_path organizes timing paths into named groups — by clock, by endpoint type, or by custom criteria — so that reporting and optimization tools can treat different classes of…

Start by reading report_timing's Incr column arc by arc to find where delay accumulates unexpectedly. The decision point at each large increment is whether it's a net arc (a…

A full setup check compares data arrival against the required time, but when launch and capture clocks share a common trunk before diverging, applying OCV derates independently…

At low operating voltage, cell delay can actually increase as temperature drops, because the threshold voltage's temperature dependence starts to dominate over the usual…

A frequency-divided clock relationship is modeled with a generated clock definition that ties the derived clock's edges to a divide ratio off the source clock, letting the tool…

A compound generated clock — one that is both divided and gated from its source — must correctly encode both operations, or the tool will compute wrong edges, wrong periods, or…

CRPR looks at the clock tree from its root down to the point where the launch and capture paths diverge, computes how much the early and late derated delays differ across that…

OCV is the phenomenon that identical devices in different locations on the same die behave slightly differently, due to random dopant fluctuation, lithography variation,…

AOCV makes the derate factor depend on path characteristics — chiefly path depth (number of stages) and sometimes distance — instead of applying one flat derate everywhere,…

POCV models variation statistically per timing arc rather than with derate factors: each arc carries a nominal delay and a standard deviation (sigma) from the library's variation…

set_timing_derate is the command that applies OCV derate factors, with qualifiers letting you target exactly which delay components (cell vs net, clock vs data) get derated and…

Crosstalk delay happens when the victim net is itself switching and the aggressor's injected current adds to or subtracts from the victim's own transition, shifting when the…

Summing individual aggressors' worst-case contributions is pessimistic because it assumes every aggressor can switch at exactly the moment needed to maximally disturb the victim,…

Based on the sampled PTUG material, PrimeTime does not include a command to create or schedule useful skew — that is implemented upstream in synthesis/CTS tools. PrimeTime's role…

set_false_path and set_max_delay define exceptions on a specific point-to-point path basis, while set_disable_timing removes timing arcs through a given pin entirely, which is…

report_timing offers extensive filtering to scope exactly which paths get reported — including multiple -through lists, -input_pins, -max_paths N, -slack_lesser_than, and…

The timing_report_union_tns variable controls whether Total Negative Slack is computed as a 'union' (true, the default) across overlapping violation categories or as 'every-…

fix_eco_timing -type setup fixes setup violations using cell sizing only, with no buffer insertion or clock-network changes by default, while fix_eco_timing -type hold uses both…

MCMM is verifying and optimizing timing across the cross-product of functional modes and analysis (PVT) corners, with each mode-corner combination forming a scenario; DMSA is the…

RC corners model interconnect extremes from process variation in wire width and spacing: Cmax (wider width, closer spacing, lower R, higher C) is setup-worst on short…

A trustworthy signoff requires working through a full checklist of analysis dimensions — corners, OCV/derating, crosstalk, MCMM scenarios, exceptions — and confirming each is…

Observing that real silicon consistently outperforms signoff timing might indicate recoverable over-pessimism worth investigating, but it can also be a dangerous…