Why a circuit needs to remember
Every circuit in the previous lesson forgets its inputs the instant they change – there is no memory of what the inputs used to be. Thus, nothing in a combinational circuit can count, hold a result across a clock cycle, or sequence a series of operations one step at a time. A sequential circuit solves this by storing state: at least one of its outputs feeds back into its own inputs, either directly or through further gates, so the circuit's present output depends on both the current inputs and whatever state was stored before. The register files, counters, and finite-state machines in the rest of this path, and in the next lesson specifically, are all built from the storage elements covered here.
The SR latch
The simplest storage element is the SR latch, built from two NOR gates with each gate's output fed back as one input to the other. It has two inputs, Set (S) and Reset (R), and keeps its state Q until told otherwise: driving S to 1 forces Q to 1 (sets it); driving R to 1 forces Q to 0 (resets it); holding both S and R at 0 leaves Q exactly where it was, which is the memory behaviour the latch exists to provide. Driving both S and R to 1 at once is forbidden – both NOR outputs are forced to 0, which violates the Q and Q′ complementary relationship the latch is supposed to maintain, and the state is undefined the moment both inputs release.
The gated D latch
An SR latch is awkward to use directly, since the designer has to remember never to assert S and R together. A D (data) latch removes the problem by deriving S and R from a single data input D and an enable signal: when enable is 1, S = D and R = D′, which can never be 1 together, and Q simply follows D; when enable is 0, both S and R are forced to 0 and Q holds its last value regardless of what D does. This is why the device is called "transparent" while enabled – the output is transparent to, or follows, the input – and "latched" once enable drops to 0.
| Enable | D | Q (next) |
|---|---|---|
| 0 | X | Holds previous Q |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
From latch to flip-flop
A level-sensitive latch is transparent for the entire time its enable is high, which is a liability the moment latches are chained: if the enable of one latch is tied to the same clock as the next, a change at the input can race straight through both latches while the clock is still high, corrupting state the circuit meant to hold. A flip-flop solves this by being edge-triggered rather than level-sensitive – it only looks at D at the instant of a clock edge – and the standard way to build one is the master-slave structure: two D latches in series, the master enabled while the clock is low and the slave enabled while the clock is high (achieved by feeding the slave's enable through an inverter from the master's).
Walking through one cycle makes the edge-triggered behaviour concrete. While CLK is low, the master is transparent and tracks D, while the slave is opaque and holds its old Q. The instant CLK rises, the master closes and freezes whatever D was at that instant, while the slave opens and copies the master's frozen value through to Q. Q therefore changes only at the rising edge of CLK, and only to the value D held at that edge – exactly the behaviour the name "edge-triggered" promises, and exactly what stops two cascaded flip-flops from racing the way two cascaded latches would.
Setup time and hold time
A real flip-flop needs D to be stable for a short interval around the triggering edge, not just stable exactly at the edge, because the internal gates need a finite time to resolve a decision. Setup time (tsu) is how long before the clock edge D must already be stable; hold time (th) is how long after the edge D must continue to be stable. Together they define a forbidden window around every triggering edge during which D is not allowed to change. Violating either one does not necessarily produce a clean wrong answer – it can instead leave the flip-flop's internal node at neither a valid 0 nor a valid 1 for an unpredictable time, a condition called metastability, which is why real designs budget timing margin specifically to keep every data transition outside this window. The timing-closure material later in this curriculum returns to setup and hold in much more depth; this lesson only needs the definition.
Key takeaways
- A sequential circuit's output depends on stored state as well as current inputs, because some output feeds back into the circuit.
- An SR latch (two cross-coupled NOR gates) holds Q when S = R = 0, sets Q to 1 when S = 1, resets Q to 0 when R = 1, and forbids S = R = 1.
- A D latch derives S and R from a single data line and an enable signal, so Q follows D while enabled and holds while disabled.
- A master-slave D flip-flop chains two D latches on opposite clock phases, making it edge-triggered instead of level-sensitive and safe to cascade.
- Setup time and hold time define a forbidden window of instability around every clock edge; violating either risks metastability rather than a clean wrong value.