📚 VLSI PHYSICAL DESIGN ARCHITECTURE SERIES
14 comprehensive mentor-led chapters — master hierarchical floorplanning, die sizing, macro placement, power network synthesis, clock trunks, 3D-IC multi-die stacking, and timing budgeting with one continuous Nimbus-8 SoC.
📖 Complete Handbook Contents (14 Chapters)
Master the core concepts of physical design planning, IC Compiler II shell automation, and splitting chip-level SDC and UPF constraints into clean block-level scopes.
What a design plan contains, how to partition a logical netlist into physical blocks, core sizing, utilization estimation, and flow readiness gates.
The IC Compiler II shell, help system, app options, units, scripts, setup files, logs, parallel work, and distributed task monitoring.
Splitting chip-level SDC and UPF constraints into top-level and block-level files, modes, corners, scenarios, and mapping files.
From initial area estimation and FinFET grid alignment to black-box IP exploration, flip-chip I/O bump arrays, and 3D-IC multi-die stacking architectures.
Floorplan styles, outline reader, initialize_floorplan, aspect ratios, rows, tracks, the FinFET grid, and resizing the die boundary.
Identifying missing or partial modules, creating black box references, target boundaries, timing models, and budgeting across blocks.
I/O rings, bump arrays and patterns, pad-to-bump assignment, corner, break, and filler cells, and RDL routing and shielding.
3DIC & 2.5D arrangements, interposers with C4 bumps and TSVs, z-levels, microbump mirroring, die-to-die channels, and check_3d_design.
Committing logical hierarchy to physical blocks, block shaping, macro placement channels, keepouts, relative constraints, and PG power mesh synthesis.
Exploring hierarchy, module boundaries, committing blocks, placement abstracts, push/pop objects, shadow netlists, and ECO scripts.
Macro constraints, keepouts, relative placement, shape_blocks, constraint files, Tcl shaping, MIB grids, and ML macro placement.
Pattern-based power planning, PG strategies, compile_pg, power rings, meshes, stdcell rails, and power integrity check rules.
Global routing corridor analysis, early CTS clock trunk latency, pin assignment and feedthrough corridors, and top-level timing budgeting signoff.
Routing corridors, global routing in design planning, congestion heatmaps, cross-block feedthrough estimation, and routing budgets.
Clock trunk architecture, early CTS latency estimation, synthesize_clock_trunks, anchor insertion, and cross-block clock tree balance.
Pin assignment, block and individual constraints, pin bundles, feedthrough routing corridors, place_pins, and pin checks.
Timing abstracts, virtual in-place optimisation (VIPO), estimated_corner, compute_budget_constraints, and budget shells.