📚 VLSI PHYSICAL DESIGN IMPLEMENTATION SERIES
8 mentor-led chapters, 693 pages, 146 vector figures — one continuous Nimbus-8 design carried from library setup and floorplanning through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO signoff, taught the way a senior engineer explains it to a new hire at their desk.
From an empty library setup to a legally placed, timing-aware design — importing the netlist and power intent, sizing the die and placing macros, and driving the five stages of place_opt to a placement the rest of the flow can build on.
Library and technology setup, netlist and power-intent import, timing setup, and the readiness checks that gate entry into floorplanning.
Die and core geometry, rows and tracks, macro placement, power-planning interfaces, and the arithmetic that turns a target density into an achievable one.
The five place_opt stages, legalization, timing/congestion-driven placement, concurrent clock/data optimization, and the reports that clear a design for CTS.
Building and balancing the clock, committing every net to metal, and turning a routed, timing-closed database into something a foundry can actually build.
What changes at CTS: defining and balancing clock trees, clock_opt, multisource clock trees, reading a clock QoR report, and troubleshooting by symptom.
Routing strategy, the standard global/detail-route flow, routing with Custom Router, postroute optimization, and the stage-exit checklist to chip finishing.
Tap, boundary and filler cells, redundant vias, critical-area reduction, metal density/fill, and signoff DRC with IC Validator In-Design, ending in stream-out.
The two things that decide whether a design tapes out on schedule: splitting a design too big to close flat into blocks that close independently, and changing a closed database without disturbing it.
Partitioning and block definition, pin assignment and feedthroughs, timing budgeting, abstract views and ETMs, and top-level closure for a hierarchical design.
Identifying what changed, the five ECO flows, spare cells/freeze silicon, the PrimeTime signoff loop, ECO Fusion, and proving an ECO disturbed nothing else.