Analog role

Analog & Mixed-Signal Design Engineer

Designs amplifiers, references, data converters, PLLs and I/O at transistor level.

Hiring demand: Medium
Best degrees: B.Tech ECE or EEE, M.Tech VLSI / Microelectronics, M.Tech in analog or RF design, MS (Research) or PhD
Time to job-ready: 9-15 months more, often during an M.Tech after the basics

Analog skills are scarce and well valued, but most openings expect an M.Tech or strong lab experience.

What the job is

An analog and mixed-signal engineer designs circuits at transistor level. You size devices for op-amps, bandgap references, ADCs, DACs, PLLs, LDOs and I/O, and you prove them across process, voltage and temperature.

Analog blocks connect the digital chip to the real world. Every SoC needs clocks, references, power management and interfaces, and these are often the hardest blocks to get right.

The work is deep and slow-building. Intuition takes years. It depends on device physics, circuit theory, simulation and careful layout.

A day in the role

Size an amplifier stage by hand using gm/ID and check it in a SPICE simulator.
Run corner and Monte Carlo simulations and study offset and gain spread.
Review layout with the layout engineer: matching, common-centroid placement and guard rings.
Run post-layout simulation with extracted parasitics and compare with schematic results.
Discuss block specifications with the system or digital team.
Document the design and its verification results.

You’ll enjoy it if

You enjoyed network theory, analog electronics and device physics.
You like hand analysis and intuition more than scripting.
You are patient with long simulation and redesign loops.
You want a deep specialty that rewards years of experience.

It may not suit you if

Analog roles usually expect an M.Tech or strong lab work, so fresher B.Tech openings are limited.
Progress is slow at first, and it takes years to be trusted with full blocks.

Skill ladder

Three stages, in order. Each ends with something you can show, not just something you studied.

Foundation4-6 months

Skills
- Semiconductor devices: MOSFET regions, threshold, body effect, channel-length modulation
- Small-signal models and gain of single-stage amplifiers
- Current mirrors and differential pairs
- Frequency response, poles and zeros
- Feedback and stability basics
- SPICE netlists and simulation
Tools
ngspiceXschemSKY130 or GF180 PDKPython for plotting

You are here when: You designed and simulated a 5-transistor OTA and a current mirror in SKY130 with ngspice, and compared hand calculations with simulation.
Job-ready9-15 months more, often during an M.Tech

Skills
- Two-stage op-amp design with Miller compensation
- gm/ID design methodology
- Noise, offset and mismatch, Monte Carlo analysis
- Bandgap references and LDOs
- Comparators and SAR ADC basics
- Layout: matching, common-centroid, guard rings, DRC and LVS
- Post-layout parasitic simulation
Tools
Xschem and ngspiceMagicKLayoutNetgenVirtuoso and Spectre (lab or M.Tech)

You are here when: A two-stage op-amp or bandgap in SKY130 or GF180 with schematic, layout, LVS-clean extraction and post-layout PVT results.
Senior6-10 years on the job

Skills
- Owning complex blocks: PLLs, high-resolution ADCs, SerDes front-ends
- Architecture trade-offs at system level
- Reliability, aging and ESD awareness
- Silicon characterization and debug
- Mixed-signal verification with digital teams
Tools
VirtuosoSpectreCalibrelab instruments

You are here when: You designed a block that worked in silicon to spec and led its characterization.

Learning path

Devices and circuitsMOSFET physics and small-signal analysis are non-negotiable.
NPTEL Analog IC DesignFree IIT courses on analog circuits and CMOS design.
Digital basics tooMixed-signal blocks have digital control. Know logic and Verilog basics.
ngspice and XschemSimulate mirrors, diff pairs and an OTA on SKY130 or GF180.
Two-stage op-ampHand design, compensate and verify across PVT corners.
Layout in MagicDraw, run DRC and LVS with Netgen, then post-layout simulate.
Consider an M.TechMost analog openings prefer it. Plan GATE EC early.
Silicon through Tiny TapeoutAnalog submissions are possible on some shuttles. Real silicon teaches the most.

Projects that prove it

More: Analog & mixed-signal projects

What interviews test

MOSFET operating regions and small-signal model
Gain, bandwidth and output resistance of CS, CG and CD stages
Current mirrors: accuracy, cascode, output resistance
Differential pair and CMRR
Two-stage op-amp compensation and phase margin
Noise: thermal and flicker, input-referred noise
Bandgap principle: PTAT and CTAT
Offset and mismatch, Pelgrom's law
Layout matching techniques
Your own design: why each transistor has its size

Mistakes freshers make

Tuning sizes in simulation without hand analysis, so start every design from equations and gm/ID.
Simulating only the typical corner, so always run PVT corners and Monte Carlo.
Stopping at the schematic, so do layout and post-layout simulation even for one block.
Skipping the M.Tech decision until final year, so plan GATE preparation from 3rd year.

Pay in India

Show as a table

Salary ranges by role, ₹ lakh per annum (indicative)
Role	Fresher to staff	3–5 years
Analog / mixed-signal	₹4–75 LPA	₹10–22 LPA

Source: semiconductor.cv VLSI Salary Guide India 2026, an aggregate of public salary sites with no stated method. Indicative only; company type, city, degree and college move these numbers a lot.

Compare all roles and read the caveats

Questions people ask

Is analog design possible with only a B.Tech?

It is possible but harder. Most analog openings expect an M.Tech or strong lab work. A B.Tech graduate with a silicon-proven or post-layout-verified project stands out.

Can I learn analog design with open-source tools?

Yes. Xschem, ngspice, Magic, KLayout and Netgen with the SKY130 or GF180 PDK give you a complete schematic-to-layout flow.

EEE or ECE for analog?

Both work. EEE gives strong circuits and power basics. ECE gives more electronics and VLSI electives. What matters most is your analog circuits depth.