Design your own chip

Every stage a chip passes through from Verilog to a signed-off GDS, and the free, open-source tool that does it. No license, no seat cost — the exact same flow a Tiny Tapeout submission uses.

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  1. 01

    RTL design + simulation

    Write Verilog and prove it works with a testbench

    Icarus VerilogVerilatorGTKWave

    Commercial Xcelium, VCS, Questa

    Output Verified RTL + waveform

    First commands to try

    • Icarus Verilog

      iverilog -o sim tb.v src/design.v && vvp sim

      Compiles the testbench and design, then runs the simulation.

  2. 03

    Synthesis

    RTL becomes a netlist of real standard cells

    YosysABC

    Commercial Genus, Design Compiler

    Output Gate-level netlist

    First commands to try

    • Yosys

      yosys -c 1_synth.tcl

      Runs the synthesis script against the sky130 cell library.

  3. 05

    Placement

    Every cell gets a legal spot; slew/cap repaired

    OpenROAD (RePlAce, resizer, detailed placement)

    Commercial Innovus, ICC2

    Output Placed DB

    First commands to try

    • OpenROAD

      openroad -exit 3_place.tcl

      Global then detailed placement, then resizer repairs slew/cap violations.

  4. 07

    Routing

    Global plan, then real metal wires and vias

    OpenROAD (FastRoute, TritonRoute)

    Commercial NanoRoute, Zroute

    Output Routed DEF/ODB

    First commands to try

    • OpenROAD

      openroad -exit 5_route.tcl

      Global routing plans tracks, then detailed routing lays real metal.

  1. 02

    Lint

    Catch width mismatches, latches and bad constructs early

    Verilator --lint-only

    Commercial Spyglass

    Output Clean RTL

    First commands to try

    • Verilator

      verilator --lint-only -Wall src/design.v

      Static-checks the RTL without simulating it.

  2. 04

    Floorplan + power grid

    Die, core, rows, pins, taps and the PDN

    OpenROAD (ifp, ppl, tapcell, pdngen)

    Commercial Innovus, ICC2

    Output Floorplanned DB

    First commands to try

    • OpenROAD

      openroad -exit 2_floorplan.tcl

      Sets die/core area, places pins and taps, builds the power grid.

  3. 06

    Clock tree synthesis

    Balanced clock buffers to every flip-flop; hold fixed

    OpenROAD (TritonCTS, repair_timing)

    Commercial Innovus CCOpt, ICC2 CTS

    Output Clock tree + timing

    First commands to try

    • OpenROAD

      openroad -exit 4_cts.tcl

      Builds the clock tree, then repairs hold on the balanced tree.

  4. 08

    Signoff

    Timing, rules and connectivity proved clean

    OpenSTA + OpenRCX (timing)Magic + KLayout (DRC)Netgen (LVS)

    Commercial Tempus/PrimeTime + StarRC, Calibre/Pegasus

    Output GDS ready for the fab

    First commands to try

    • OpenSTA

      sta -exit 6_sta.tcl

      Extracts parasitics with OpenRCX and reports setup/hold on the routed design.

    • Magic

      magic -dnull -noconsole -rcfile sky130A.magicrc drc.tcl

      Runs design-rule checks against the GDS.

    • Netgen

      netgen -batch lvs "layout.spice layout" "netlist.spice netlist" setup.tcl lvs.report

      Confirms layout and schematic circuits match uniquely.

FromRTLtoGDS
Write Build Verify

Flow manager

Toolbox: LibreLane 3.0.17 installs every tool through Nix. The guide runs each stage by hand with its own small script.

Process kit (PDK)

SkyWater sky130 (130 nm), fetched with ciel into ~/pdk/sky130A. GF180MCU and IHP SG13G2 are other open PDKs.

What's inside the free guide

Every result comes from a real run: setup slack +7.25 ns, positive at tt, ss and ff corners, DRC 0, LVS: circuits match uniquely.

See the 13 projects built on this flow →

Learn the full flow with real commands, scripts and a working demo.

Free guide + kit · 56 pages

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