Back-end path

Physical Design

Plan a floorplan and power grid, run placement, clock tree synthesis and routing in ICC2, then qualify an Innovus run, one chapter at a time. All three handbooks are free to read online.

38
lessons
Intermediate
level
Free
every lesson
Start with lesson 1 →

Design planning

  1. 1Ch 1: What a Design Plan IsWhat a design plan contains, how to partition a logical netlist into physical blocks, core sizing, utilization estimation, and flow readiness gates.
  2. 2Ch 2: Living in the ShellThe IC Compiler II shell, help system, app options, units, scripts, setup files, logs, parallel work, and distributed task monitoring.
  3. 3Ch 3: Splitting ConstraintsSplitting chip-level SDC and UPF constraints into top-level and block-level files, modes, corners, scenarios, and mapping files.
  4. 4Ch 4: Floorplan ExplorationFloorplan styles, outline reader, initialize_floorplan, aspect ratios, rows, tracks, the FinFET grid, and resizing the die boundary.
  5. 5Ch 5: Handling Black BoxesIdentifying missing or partial modules, creating black box references, target boundaries, timing models, and budgeting across blocks.
  6. 6Ch 6: I/O & Flip-Chip PlanningI/O rings, bump arrays and patterns, pad-to-bump assignment, corner, break, and filler cells, and RDL routing and shielding.
  7. 7Ch 7: 3DIC & Multi-Die Design3DIC & 2.5D arrangements, interposers with C4 bumps and TSVs, z-levels, microbump mirroring, die-to-die channels, and check_3d_design.
  8. 8Ch 8: Managing Design BlocksExploring hierarchy, module boundaries, committing blocks, placement abstracts, push/pop objects, shadow netlists, and ECO scripts.
  9. 9Ch 9: Block Shaping & MacrosMacro constraints, keepouts, relative placement, shape_blocks, constraint files, Tcl shaping, MIB grids, and ML macro placement.
  10. 10Ch 10: Power Planning & PGPattern-based power planning, PG strategies, compile_pg, power rings, meshes, stdcell rails, and power integrity check rules.
  11. 11Ch 11: Global Planning & RoutingRouting corridors, global routing in design planning, congestion heatmaps, cross-block feedthrough estimation, and routing budgets.
  12. 12Ch 12: Clock Trunk PlanningClock trunk architecture, early CTS latency estimation, synthesize_clock_trunks, anchor insertion, and cross-block clock tree balance.
  13. 13Ch 13: Pin Assignment & BundlesPin assignment, block and individual constraints, pin bundles, feedthrough routing corridors, place_pins, and pin checks.
  14. 14Ch 14: Timing Budgeting & SignoffTiming abstracts, virtual in-place optimisation (VIPO), estimated_corner, compute_budget_constraints, and budget shells.

ICC2 implementation flow

  1. 15Ch 1: Preparing the DesignLibrary and technology setup, netlist and power-intent import, timing setup, and the readiness checks that gate entry into floorplanning.
  2. 16Ch 2: Creating the FloorplanDie and core geometry, rows and tracks, macro placement, power-planning interfaces, and the arithmetic that turns a target density into an achievable one.
  3. 17Ch 3: Placement & OptimizationThe five place_opt stages, legalization, timing/congestion-driven placement, concurrent clock/data optimization, and the reports that clear a design for CTS.
  4. 18Ch 4: Clock Tree SynthesisWhat changes at CTS: defining and balancing clock trees, clock_opt, multisource clock trees, reading a clock QoR report, and troubleshooting by symptom.
  5. 19Ch 5: Routing & Postroute OptRouting strategy, the standard global/detail-route flow, routing with Custom Router, postroute optimization, and the stage-exit checklist to chip finishing.
  6. 20Ch 6: Chip Finishing & DFMTap, boundary and filler cells, redundant vias, critical-area reduction, metal density/fill, and signoff DRC with IC Validator In-Design, ending in stream-out.
  7. 21Ch 7: Hierarchical ImplementationPartitioning and block definition, pin assignment and feedthroughs, timing budgeting, abstract views and ETMs, and top-level closure for a hierarchical design.
  8. 22Ch 8: ECO FlowIdentifying what changed, the five ECO flows, spare cells/freeze silicon, the PrimeTime signoff loop, ECO Fusion, and proving an ECO disturbed nothing else.

Innovus qualification

  1. 23Innovus Session and Project QualificationBefore a single cell is placed, we need to know which tool, which interface, which inputs and which settings produced the numbers we are about to read.
  2. 24Innovus Design Import and Database SanityDesign import and database sanity.
  3. 25Innovus SDC and MMMC Timing QualificationSDC, MMMC and timing-environment qualification.
  4. 26Innovus Floorplan, Macro and Pin ChecksFloorplan, macro and pin qualification.
  5. 27Innovus Power Planning QualificationPower planning builds the supply network that every later stage depends on and that every later stage must route around.
  6. 28Innovus Pre-Placement Readiness ChecksPlacement is the first stage that cannot be repaired by editing the floorplan alone, because it moves every cell that is not fixed.
  7. 29Innovus Placement Qualification ChecksPlacement and post-placement qualification.
  8. 30Innovus Clock Tree Synthesis ReadinessClock tree synthesis readiness.
  9. 31Innovus CTS and Post-CTS QualificationClock tree synthesis replaces an ideal clock with a real network of buffers, wires and gates, and every later timing number depends on it.
  10. 32Innovus Global and Early Routing ChecksPlacement and clock tree synthesis decide where cells and clock wires go.
  11. 33Innovus Detailed Route QualificationDetailed-route qualification.
  12. 34Innovus Post-Route Optimisation ChecksAfter detailed routing the wires are real, so the delays are real too, and some of them are worse than the plan assumed.
  13. 35Innovus Chip Finishing and Post-Fill ChecksChip finishing and post-fill qualification.
  14. 36Innovus Extraction and Signoff CorrelationEvery delay after routing rests on the resistance and capacitance that an extractor reads from the wires.
  15. 37Innovus ECO and Incremental RequalificationECO and incremental requalification.
  16. 38Innovus Final Implementation HandoffHandoff is the point where the implementation database stops being a working session and becomes a set of files that other teams and tools read.