What synthesis really does

Synthesis is the first step in the flow where a design stops being a description and starts being a circuit. The tool reads RTL, which only says what the design should do, and produces a netlist of standard cells from a technology library, which says exactly which gates will be built. Everything after this step, floorplanning, placement, clock tree synthesis and routing, works on that netlist.

Reading time: about 7 minutes.

1.1 One RTL, many netlists

Let us consider a single line of RTL, assign y = a + b; with 8-bit operands. The line does not say whether the adder should be a ripple chain, a carry-lookahead structure or something in between. A ripple adder is small and slow. A lookahead adder is larger and fast. Both are correct.

The tool picks one. It picks based on how much time the path has, which is why the same RTL can give a small netlist at 100 MHz and a larger one at 500 MHz. Thus, synthesis is not a translation. It is a search for the smallest implementation that still meets the timing the designer asked for.

1.2 The three inputs

Every synthesis run needs three things, and a missing one usually shows up as a wrong result rather than an error.

• RTL – the behaviour, written in Verilog, SystemVerilog or VHDL.
• Technology library – a Liberty (.lib) file that lists every cell the foundry offers, with its area, delay tables, pin capacitances and power. The tool can only use cells that appear here.
• Constraints – the clock period, the delays at the ports, and the exceptions. These are normally written in SDC (Synopsys Design Constraints) format. These describe things outside the design that the tool cannot work out itself.

If the library is the menu, the constraints are the order. A tool given RTL and a library but no clock has no idea how fast the design must run, so it treats the paths as unconstrained and optimizes mainly for area, which makes its timing reports meaningless.

1.3 What happens inside

Synthesis is performed in stages, and most tools, Genus included, expose them as separate commands.

1. Elaboration – the RTL is parsed and turned into a generic structure of registers, muxes, adders and logic. Parameters are resolved here.
2. Generic synthesis – technology-independent optimization. Redundant logic is removed and arithmetic is restructured, but no library cell has been chosen yet.
3. Mapping – each generic function is matched to cells in the library, and the tool optimizes against the timing, area and power targets.
4. Incremental optimization – a final pass that fixes remaining violations by resizing cells, buffering nets and restructuring small pieces of logic.

Figure 1.1 shows the flow.

1.4 What comes out

The main output is the gate-level netlist. Along with it, the designer normally takes three more things away.

• The constraints, written back out in SDC, so the next tool sees exactly what synthesis used.
• Reports – timing, area, cell usage and power estimates – which say whether the run was good enough.
• Sometimes an SDF (standard delay format) file, for timing-annotated gate-level simulation.

We will write these out in Lesson 11. For now the point is that the netlist alone is not the deliverable. The netlist, the constraints and the reports travel together.

1.5 Ideal wires and ideal clocks

At this stage the tool does not know where cells will be placed. Wire delays are therefore estimated, and the clock network is treated as ideal, meaning the clock reaches every register at the same moment with no delay and no skew. This is a modelling choice. The real clock tree is built later, during clock tree synthesis, and the designer usually adds a small uncertainty to the clock now to leave room for it.

A consequence worth remembering is that timing met at synthesis is a promise, not a proof. A design that has no violations here might still fail after placement. Hence, synthesis targets are often set slightly tighter than the final goal.

1.6 The tools

Cadence Genus and Synopsys Design Compiler are two widely used commercial tools. Their command names differ, but the ideas in this path carry over directly. We use Genus commands in the lessons, and where it helps, a free alternative, Yosys with an open Liberty library, so that the exercises can be run without a licence.

Different tools treat some options differently. When a behaviour matters, check the help for your own tool version before relying on it.

1.7 Why an interviewer asks about this

Interviewers start here because the answer shows whether a candidate sees synthesis as translation or as optimization under constraints. A candidate who can say that the same RTL gives different netlists at different clock periods, and who can name the three inputs, has the right picture. Expect follow-ups such as "what happens if you give no clock constraint?" and "why does the tool treat the clock as ideal?"