OCV, AOCV, POCV, and CRPR in STA Timing Signoff: Complete Guide
In deep submicron and sub-7nm FinFET silicon fabrication, standard cells and interconnect wires experience substantial physical variation (oxide thickness, channel length, dopant fluctuations). This guide covers how STA tools transition from flat OCV to AOCV and Parametric On-Chip Variation (POCV/LVF) with Clock Reconvergence Pessimism Removal (CRPR).
1. Flat On-Chip Variation (OCV) & Limitations
In mature silicon nodes (>65nm), on-chip process, voltage, and temperature variations across a single die were accounted for using Flat OCV. Designers applied uniform scaling factors via set_timing_derate:
set_timing_derate -early 0.92
set_timing_derate -late 1.08
While straightforward, Flat OCV is inherently non-physical for deep submicron designs: it treats every gate along a 30-stage clock tree as if it independently suffers worst-case variation in the same direction, accumulating artificial timing pessimism that forces severe over-design and power waste.
→ Practice Full Q&A: OCV foundations and signoff derating rationale2. Advanced OCV (AOCV) & Depth Derates
Advanced On-Chip Variation (AOCV) resolves flat OCV pessimism by computing derate factors as a mathematical function of path logic depth (number of gates) and bounding box distance. Because random statistical variations cancel each other out over long inverter/buffer chains (by the central limit theorem), AOCV applies smaller derates to deep paths and larger derates to shallow paths.
→ Practice Full Q&A: AOCV depth-based derating vs Flat OCV3. Parametric OCV (POCV) & Liberty Variation Format (LVF)
At advanced FinFET nodes (16nm, 7nm, 5nm, 3nm), variation is non-linear and dominated by threshold voltage fluctuations and line edge roughness. Modern timing flows utilize Parametric OCV (POCV) or Statistical OCV (SOCV) paired with Liberty Variation Format (LVF).
In POCV, each standard cell timing arc in the library contains a nominal delay ($D_{nom}$) and a normalized sensitivity/variation parameter ($sigma$). The actual cell delay is evaluated as:
Where C is the signoff sigma multiplier (typically 3σ for 99.73% statistical yield).
Because cell delays along a path are statistically independent random variables, total path variation is summed via Root-Sum-of-Squares (RSS):
4. Common Path Pessimism Removal (CRPR / CPPR)
When analyzing a register-to-register timing path, the launch clock path and capture clock path frequently share a substantial segment of the clock distribution network from the clock root source to the common divergence point (such as a clock gating cell or root buffer).
During timing analysis with derates, the STA tool derates the common clock tree cells with a late multiplier for the launch edge and an early multiplier for the capture edge. In reality, a physical gate cannot exhibit two different delays for the exact same transition. Clock Reconvergence Pessimism Removal (CRPR) calculates this artificial difference and adds it back as positive timing credit.
Setup Slack_adjusted = Setup Slack_raw + CRPR Credit
6. Core Variation Interview FAQs
Why does Flat OCV become overly pessimistic on deep clock trees?
Flat OCV applies a fixed percentage derate (e.g. ±10%) across every cell in the path. In reality, random uncorrelated variations average out as path logic depth increases (law of large numbers). Flat OCV ignores this statistical averaging, demanding excessive silicon margins.
What is the purpose of Clock Reconvergence Pessimism Removal (CRPR)?
When launch and capture clock paths share common clock buffers, static timing analysis derates the common segment as late for launch and early for capture simultaneously. CRPR calculates and removes this impossible physical divergence.
How does POCV calculate total path delay variance?
Under POCV, each standard cell delay is modeled as Nominal + C * Sigma. Because random variations are independent, total path variation combines through root-sum-of-squares (RSS): Sigma_path = sqrt(sum(Sigma_i^2)).