What this chapter covers

Not all timing is register-to-register. Combinational feedthroughs and point-to-point requirements use set_max_delay/set_min_delay. Designs also operate in multiple modes (functional, test, low-power) where the same netlist is constrained differently via case analysis and mode-specific SDC. Special checks include data-to-data, min pulse width, clock gating, and combinational loops.

Closing timing means closing the mode×corner grid, not only the “happy functional” view. Case analysis is how a tied select or scan-enable constant legally disables arcs for that mode.

Worked example

set_case_analysis 0 [get_ports scan_en] in a functional view disables scan-shift arcs so you do not time scan paths as functional. A combinational I/O feedthrough may need set_max_delay referenced to the right clocks because there is no capturing flop inside the block.

A common misconception

Leaving case analysis from a test view in the functional view (or vice versa), so the wrong arcs are timed. Using set_max_delay as a disguised false path. Ignoring combinational loops that check_timing flagged.

Sample interview answers

When do you use set_max_delay instead of a clocked setup check? When there is no natural launch/capture pair inside the design (combinational feedthrough, analog boundary, or an explicit point-to-point budget).

What does set_case_analysis do? It pins a signal to a constant for that analysis view so disabled mux arcs and constants propagate — matching one operating mode.

Why must every mode be closed? Clocks, exceptions, and valid paths change with mode. A functional-only signoff can miss scan or low-power timing that still ships in silicon.

The paid PDF covers max/min delay versus MCP, case analysis, MCMM scenario construction, special checks, and the chapter interview set.

MMMC: MMMC timing signoff · Next: Managing constraints · Related: What is a mode?, MMMC questions

💡 Key Technical Topics Covered

  • set_case_analysis (Logic 0, 1, Rising, Falling)
  • set_disable_timing for Breaking Feedback Loops
  • Func vs Test Mode Constraint Management
  • Combinational Path Delay Constraints (set_max_delay)

🎯 VLSI Physical Design Interview Questions Addressed

  • How do you use set_case_analysis to disable test mode during functional STA?
  • What is set_disable_timing and when is it safe to use?
  • How do you constrain purely combinational paths in SDC?