MMMC Interview Questions and Answers

MMMC stands for Multi-Mode Multi-Corner analysis — running timing across every operating mode and physical condition the chip must survive, instead of just one. We need it…

A mode describes what the chip is doing right now — running its real function, shifting scan data during test, capturing a test response, or sitting in a low-power state. The…

A mode answers "what is the chip doing?" A corner answers "under what physical or electrical condition is it doing it?" They are two completely separate questions, and a real…

A constraint mode is the bundle of timing intent — clocks, generated clocks, input/output delays, exceptions, case analysis, clock groupings — that applies to one specific mode.…

It's not that using one file is physically impossible — you could write it. The real problem is that different modes can require genuinely different timing intent, and cramming…

Process, Voltage, Temperature — the three physical and electrical conditions that determine how fast or slow a manufactured cell actually behaves compared to its nominal design…

Because delay isn't a stored number — it's the output of a function that depends on the PVT condition, the input transition (slew), the output load, which specific timing arc is…

A timing library (typically in Liberty format) is the characterized model of how a specific cell behaves electrically — its pins, its logic function, and tables of delay,…

Slew is how fast a signal transitions between logic levels — a sharp, fast edge versus a slow, lazy one. A slower input edge makes the receiving cell switch more gradually, which…

Output load is the total capacitance a driving cell has to charge or discharge on its output — the receiving pin's own input capacitance plus whatever the connecting wire adds. A…

Parasitics are the unavoidable electrical side effects of a physical wire — resistance along its length, capacitance to the ground plane and other reference layers, and coupling…

Because a real wire has distributed resistance and capacitance along its length, not one lump sum at the end. Each little segment of the wire has its own R and C, so a signal…

SPEF (Standard Parasitic Exchange Format) is the file format used to hand off extracted interconnect parasitics — resistance, ground capacitance, and coupling capacitance for…

An RC corner is a named, characterized interconnect condition — a set of assumptions about wire resistance and capacitance — used consistently across the flow. If the timing…

A library set is a named, consistent group of timing libraries — standard cells, memories, I/O, and any hard macros — that all belong to the same cell timing condition. It exists…

A delay corner is the combination of a library set (how the cells behave) and an RC corner (how the wires behave) into one unified condition for computing delay. It answers, in…

No. A delay corner only describes the cell-plus-wire condition. Whether that condition is used for a setup check, a hold check, or both is decided separately, when the delay…

An analysis view is the complete, named timing world an STA engine actually analyzes — built by pairing one constraint mode (the timing intent) with one delay corner (the…

Setup checks whether data launched from one flop arrives at the next flop early enough to be captured correctly on the upcoming clock edge. Hold checks whether that same data…

At minimum: a netlist for connectivity, timing libraries for cell behavior, an SDC for timing intent, parasitic data for interconnect behavior, and an MMMC configuration that…

Because "the same path" is only the same topology — it isn't the same electrical or timing condition. Change the mode, the corner, or both, and you change the active clocks, the…

Yes, and it usually should be. A constraint mode captures timing intent for one behavior (say, functional mode), and that same intent commonly needs to be checked against several…

Yes. A delay corner only describes a cell-plus-wire physical condition — it has no idea what behavior the chip is performing. So the same delay corner can legitimately pair with…

Because the actual worst-case check depends on the full launch-and-capture relationship, the interconnect condition, temperature behavior (including inversion effects at some…

Creating a view just registers it as an object that exists in the database — it doesn't participate in any check yet. Activating it (declaring it as part of the setup list, the…

It means that view is contributing nothing to the current timing results, no matter how correctly it was built. If your signoff plan requires that condition to be checked, and…

Start from the environment, not the cell. Confirm which view or scenario is failing, then work outward: is the mode correct, is the SDC correct, is the library/PVT correct, is…

They solve the same underlying problem — combining behavior and physical condition into one complete timing world — but they are not the same database object, and their commands…

Because pre-route timing uses estimated interconnect, and actual routing can introduce longer detours, extra vias, different layer assignments, more coupling exposure, and…

View explosion is the uncontrolled growth of the Cartesian product of modes, cell conditions, and RC conditions into far more combinations than are actually meaningful. Analyzing…

Nothing is wrong with the timing engine. The physical change you made — a resize, a buffer insertion, whatever it was — is global. It affected every view that touches that cell…

This is almost never "the signoff tool is being pessimistic." It's much more likely a correlation gap — a mismatch somewhere between what ICC2 analyzed and what PrimeTime…

The run environment, before you ever suspect tool instability. Compare SDC, library versions, parasitic extraction/revision, derating and SI settings, clock definitions, and tool…

No. A successful file read only proves the parser accepted the file — it says nothing about whether every net was correctly matched, mapped, and actually consumed by the delay…

Because a cell's delay depends on its output slew, and output slew depends on the load it drives — which includes the interconnect. Change the RC, and you change the effective…

Because WNS is only one lens on risk. A view can be required for unique endpoints, a specific check type, a distinct optimization stage, or regulatory/product coverage reasons…

GBA propagates conservative, graph-level worst-case assumptions efficiently across the whole design; PBA recalculates a specific path with path-specific context, removing some of…

Because SI introduces a new dependency that plain nominal timing doesn't capture: coupling between neighboring nets, which depends on aggressor switching alignment, direction,…

The configured object associations — not the human-readable name. The engine doesn't parse the name string for meaning; it uses whatever library, RC corner, and constraint mode…

Which modes, which corners, which setup views, which hold views, and were all the views required by the signoff plan actually active. Which libraries and RC/parasitic data were…