What this chapter covers

By default, data launched from a register must be captured in one cycle. A multicycle path (MCP) is a path the design guarantees is allowed N cycles. SDC uses setup and hold multipliers; relaxing setup without moving hold is the classic error. An MCP relaxes timing — it does not remove the check.

Slow datapaths held stable across cycles, periodic compute results, and some integer-ratio crossings are legitimate MCPs. The RTL or protocol must actually wait N cycles; the constraint cannot invent that behavior.

Worked example

A path allowed two cycles for setup typically uses set_multicycle_path 2 -setup and set_multicycle_path 1 -hold (the usual pairing that moves the hold check back to the original edge). The exact hold multiplier depends on edge alignment; copying “MCP 2” without a hold adjustment produces a flood of false hold failures or a real hold hole.

A common misconception

Setting only the setup multiplier. Setup moves the required edge later; hold, if left at default, is still checked to the same-cycle edge and becomes impossibly tight — or, if someone then false-paths hold, a real short-path risk. Another trap: MCP on a path that is not actually sampled late in the design.

Sample interview answers

Does a multicycle path disable timing? No. It changes which launch/capture edges are used. The path is still checked, with more time for setup if the design really waits.

Why is a hold multiplier usually required with setup MCP? Moving the setup capture edge without adjusting hold leaves a same-cycle hold check that no longer matches the intended sampling.

How do you verify an MCP? report_timing on that path should show the intended cycle count in the required-time stack, and the RTL/protocol must match that count.

The paid chapter works the setup/hold cycle-count diagram, default versus explicit hold multipliers, report_timing checks for MCP, and 80 interview questions.

Previous: False paths · Next: Combinational and modal analysis · Related: STA interview questions

💡 Key Technical Topics Covered

  • set_multicycle_path Setup Multiplier (-setup)
  • set_multicycle_path Hold Correction (-hold)
  • Enable-Controlled Flip-Flop Multicycle Timing
  • Phase Shifted Multicycle Constraints

🎯 VLSI Physical Design Interview Questions Addressed

  • Why must you specify a hold multicycle constraint whenever you set a setup multicycle path?
  • How do you constrain a 2-cycle multicycle path in SDC?
  • What happens if you omit set_multicycle_path -hold?