What this chapter covers

Most clocks on a chip are derived: divided by counters, multiplied by PLLs, or gated. A generated clock is how SDC records that derivation and, crucially, the phase relationship to the master. This chapter covers create_generated_clock with -divide_by, -multiply_by, or -edges, master relationships, duty-cycle changes, and where to define the clock so downstream edges match silicon.

Every divider, PLL output, gated clock, and clock mux needs a generated-clock definition at the right pin. Cross-domain paths between master and derived clocks are only timed correctly if that relationship exists.

Worked example

A divide-by-2 flop clocked by clk should be create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins u_div/Q], not a second independent create_clock on Q. The independent clock has no phase relationship, so paths between clk and clk_div2 are treated as unrelated domains.

A common misconception

Using create_clock on a divided pin “because it has a period.” That silently mis-times every path that should have been a synchronous ratio. Another error is defining the generated clock before the divider or gate, so the waveform does not match the pin that actually fans out.

Sample interview answers

Why not create_clock on a divided output? The tool then treats it as an unrelated clock and loses the edge alignment STA needs for master–generated paths.

What does -divide_by 2 actually change? It derives the generated waveform from the master’s edges at half the frequency, keeping a defined phase relationship at the source pin you named.

Where should the generated clock be defined? At the pin that represents the clock after the divide/gate/mux, matching what downstream sequential cells actually see.

The paid chapter includes edge-relationship diagrams, PLL/divide/gate examples, latency of generated clocks, regenerated clocks, and 80 interview questions.

Previous: Clock constraints · Next: Clock groups · Related: Generated clocks versus create_clock, Frequency crossings

💡 Key Technical Topics Covered

  • create_generated_clock Syntax & Master Clock Reference
  • Frequency Divider Clocks (-divide_by)
  • Phase Shifted Clocks (-edge_shift)
  • Inverted Clocks (-invert)

🎯 VLSI Physical Design Interview Questions Addressed

  • Why must you use create_generated_clock instead of create_clock on PLL/Divider outputs?
  • How do you constrain a frequency divider by 4 in SDC?
  • What happens if master clock source pin is incorrect in generated clock constraint?