💡 Key Technical Topics Covered
- create_generated_clock Syntax & Master Clock Reference
- Frequency Divider Clocks (-divide_by)
- Phase Shifted Clocks (-edge_shift)
- Inverted Clocks (-invert)
🎯 VLSI Physical Design Interview Questions Addressed
- Why must you use create_generated_clock instead of create_clock on PLL/Divider outputs?
- How do you constrain a frequency divider by 4 in SDC?
- What happens if master clock source pin is incorrect in generated clock constraint?