What this chapter covers

A multi-clock design must declare how clocks relate: which pairs are synchronous and should be timed, which are asynchronous (CDC, not STA-timed as related), and which are mutually exclusive (never active together). The main command is set_clock_groups with asynchronous, logically exclusive, or physically exclusive relationships. The default is that clocks are related and timed against each other.

Every modern SoC has clock families, asynchronous boundaries, and muxed exclusive clocks. Constraint reviews look for both under-declaration (false CDC violations) and over-declaration (real synchronous paths cut).

Worked example

Two PLL families that never share a cycle-accurate relationship: set_clock_groups -asynchronous -group {clk_a*} -group {clk_b*}. Two mux inputs that cannot both be on: -logically_exclusive (or physically exclusive when the mux is a physical one-hot select). Generated clocks usually stay in the same group as their master unless you have a real reason not to.

A common misconception

Cutting a real synchronous crossing as asynchronous to clean CDC noise — that path will not be timed. The opposite error is leaving truly async clocks related, which floods the report with meaningless setup/hold. Exclusive is not the same as asynchronous.

Sample interview answers

What is the default relationship between two create_clock clocks? They are assumed related and STA will time crossings unless you declare otherwise with clock groups or exceptions.

When is -asynchronous appropriate? When there is no cycle-accurate relationship and the crossing is handled by CDC (synchronizers), not by STA setup/hold between those clocks.

How is logically exclusive different from asynchronous? Exclusive clocks are not on at the same time, but each may still be synchronous to something else. You are not declaring a CDC boundary; you are pruning illegal simultaneous modes.

The paid PDF works through the three relationship types, group-versus-pair pitfalls, generated-clock membership, and 80 interview questions on CDC intent versus STA.

Previous: Generated clocks · Next: I/O delays · Related: Multi-clock timing, STA questions

💡 Key Technical Topics Covered

  • Asynchronous Clock Domain Crossing (CDC)
  • set_clock_groups (-asynchronous vs -logically_exclusive)
  • Physically Exclusive Muxed Clocks
  • Crosstalk Exclusion on Clock Domains

🎯 VLSI Physical Design Interview Questions Addressed

  • What is the difference between -asynchronous and -logically_exclusive in set_clock_groups?
  • How do you constrain multiplexed clocks sharing the same clock tree?
  • Why is set_clock_groups preferred over global set_false_path between clocks?