What this chapter covers

Clocks are the heartbeat of a synchronous design. In SDC the clock definition is the constraint everything else depends on: I/O delays, setup and hold, exceptions, and the timing report’s launch and capture edges. This chapter covers create_clock (period and waveform), source versus network latency, uncertainty as margin for a real clock network, and transition/slew on clock pins.

The clock section of an SDC is written first and reviewed most carefully. Block bring-up, timing signoff, and constraint reviews all start with whether the clocks are complete and physically meaningful.

Worked example

A 100 MHz clock with a 40/60 duty cycle (40% high) is create_clock -name CLK -period 10 -waveform {0 4} [get_ports clk]: rise at 0 ns, fall at 4 ns. A 60% high wave would use {0 6}. Period is always in the SDC time unit (usually ns).

A common misconception

Confusing latency with uncertainty. set_clock_latency models when the edge actually arrives (source latency of the chip input, network latency through the tree). set_clock_uncertainty is a guardband (jitter, residual skew, extra margin) that tightens setup and hold — it is not a substitute for a missing clock tree. Another trap: leaving pre-CTS uncertainty after CTS has been propagated.

Sample interview answers

How do you constrain a 40/60 duty-cycle clock? Set the waveform edges inside the period. For period 10 and 40% high: -waveform {0 4}. Duty cycle is not a separate SDC keyword; it is implied by the rise/fall pair.

What is the difference between set_clock_latency and set_clock_uncertainty? Latency is modeled arrival of the clock edge (source and/or network). Uncertainty is extra margin subtracted from setup required time and added to the hold requirement. They are not interchangeable.

How does uncertainty change pre-CTS versus post-CTS? Pre-CTS the tree is unknown, so uncertainty often includes estimated skew. After CTS you propagate network latency (or use extracted clocks) and reduce uncertainty to residual jitter and explicit margin.

The 74-page PDF adds the full concept primer, waveform/latency/uncertainty/transition diagrams, pre- versus post-CTS methodology, 80 interview questions across four levels, and the chapter’s command/definition sheets.

Previous: SDC fundamentals · Next: Generated clocks · Related: create_clock, Clock skew, STA interview questions

💡 Key Technical Topics Covered

  • create_clock Command Parameters
  • Clock Latency (Source vs Network Latency)
  • Clock Uncertainty & Jitter Constraints
  • Clock Transition Slew Constraints

🎯 VLSI Physical Design Interview Questions Addressed

  • How do you constrain a clock with 40/60 duty cycle in SDC?
  • What is the difference between set_clock_latency and set_clock_uncertainty?
  • How does clock uncertainty change pre-CTS vs post-CTS?