Design-Technology Co-Optimization

Every lesson in this path so far has moved in one direction: physics (2-5) to simulation (6-7) to variability and the compact model (8-9), ending at a PDK a design team uses without needing to revisit the device physics underneath it. This closing lesson is about a feedback loop that runs the other way: design-technology co-optimization (DTCO), where decisions about the technology itself, the device structure, the interconnect stack, the standard cell architecture, are made jointly with an eye on how a real design will actually use them, rather than defining the technology first and handing it to design second.

Reading time: about 8 minutes.

10.1 What DTCO means

Historically, a technology node's device structure was largely finalized, then standard cell libraries and design rules were built on top of whatever that device structure happened to produce. DTCO inverts part of that sequence: because the ultimate goal of any device or process decision is area, power and performance in a real chip, not an isolated transistor's own benchmark numbers, DTCO evaluates device and process options directly in terms of their predicted impact on a representative standard cell, or even a representative block of real logic, rather than purely on isolated device metrics like Id-Vg curves in a vacuum. A device change that improves an isolated transistor's benchmark Ion/Ioff ratio but, once laid out in an actual standard cell with real wiring and real neighboring cells, does not translate into a smaller or faster cell, is exactly the kind of result DTCO is meant to catch before a technology is finalized, not after.

10.2 Cell track height as a joint decision

A standard cell's track height (the cell's height, measured in the number of horizontal routing tracks it spans) is a central DTCO decision, because it couples device structure and design density directly. A taller cell has more room: more fins or wider nanosheets per device (more drive current), more routing tracks for internal cell wiring, generally easier to design and characterize. A shorter cell packs more logic per unit area, improving density, but constrains how much device width and internal routing a cell can fit, which can limit achievable drive strength or routing congestion if pushed too far. Track height is therefore not decided purely on the device side (how wide can a fin or nanosheet practically be made) or purely on the design side (how dense do we want cells to be); it is decided jointly, informed by simulating how real representative cells and blocks behave at candidate track heights before committing one to the technology's PDK and design rules.

10.3 Scaling boosters: backside power and buried rails

As lateral device scaling becomes harder (lesson 5's CFET discussion already touched on this), DTCO has increasingly looked at the interconnect stack, not just the device, for further area and performance gains, under the umbrella term scaling boosters. Two prominent examples:

• Buried power rails (BPR): rather than routing a standard cell's power and ground rails in the same metal layers as signal routing (competing for the same limited routing resources at the cell boundary, as conventional BEOL power delivery does), a buried power rail is built into the substrate itself, below the active devices, freeing up the signal routing layers that power rails previously occupied and allowing cells to be packed more tightly without power routing congestion limiting that density.
• Backside power delivery: a more extensive version of the same idea, moving the entire power delivery network to the back side of the wafer (processed after flipping and thinning the wafer from the back), physically separated from the signal routing on the front side entirely. This frees essentially all front-side BEOL metal layers for signal routing, and can also improve IR drop (power delivery network resistance, a topic covered in this site's physical design material) because power rails on the back side can be made wider and thicker without competing with signal routing at all.

Both are evaluated through the same DTCO lens as track height: their benefit is measured in terms of real cell and block-level density, power delivery quality and routing congestion, not as an isolated process capability evaluated on its own.

10.4 How DTCO reaches physical design

DTCO decisions, track height, scaling boosters, device structure choices, ultimately show up to a physical design engineer as the technology's design rules, the standard cell library's available cell heights and drive strengths, and the PDK's power delivery assumptions, all topics this site's physical design material covers from the design side. A physical designer does not typically participate in DTCO directly, but every constraint that physical design, placement, routing, power planning, works within, cell height, routing layer stack, where power rails live, is itself the output of a DTCO process that evaluated those choices against representative real designs before the technology was finalized. This is the thread connecting this entire Device & TCAD path back to the rest of the site's VLSI content: the numbers and rules taken for granted in RTL, synthesis, physical design and STA all trace back, through this path, to decisions made here.

10.5 Interview questions

What does DTCO mean, in one sentence? Evaluating device and process technology decisions jointly with their impact on real standard cells and blocks, rather than finalizing device technology first and handing it to design second.

Why is cell track height a joint device/design decision, not a purely device or purely design one? It directly trades off device width (and therefore drive strength) and internal routing room against cell density; neither the device side nor the design side alone can determine the right trade-off without evaluating how real cells and blocks actually behave at a candidate height.

What problem do buried power rails solve? They move power/ground routing out of the signal metal layers at the cell boundary into the substrate itself, freeing signal routing resources that power rails previously competed for, allowing denser cell packing.

How does backside power delivery differ from buried power rails, and what additional benefit can it bring? It moves the entire power delivery network to the back side of the wafer, not just below the active devices, freeing essentially all front-side metal for signal routing, and can improve IR drop because back-side power rails can be made wider and thicker without competing with signal routing at all.

Why does a physical design engineer who never does DTCO directly still depend on it? Every constraint physical design works within, cell heights, available drive strengths, routing layer stack, power delivery assumptions, is itself the output of DTCO decisions made before the technology was finalized.