Variability and Reliability

Every lesson so far has treated a device's characteristics, threshold voltage, on-current, subthreshold swing, as single numbers predicted or measured for one nominal device. Real chips contain billions of nominally identical transistors, and no two are electrically identical; this lesson covers why, splitting the causes into two categories: variability (device-to-device differences that exist from the moment the chip is manufactured) and reliability (how a device's characteristics drift over its operating lifetime). Both categories are exactly why signoff timing analysis, covered elsewhere on this site, runs at multiple corners and includes aging margins, rather than analyzing a single nominal device.

Reading time: about 9 minutes.

8.1 Random dopant fluctuation

Lesson 2.2 described doping as a controlled average concentration. At the scale of a modern transistor's channel, the actual number of dopant atoms present is a comparatively small, discrete number, and that number, and the exact position of each atom, varies randomly from one transistor to its neighbor, even though both were implanted with the identical intended dose and energy. This random dopant fluctuation (RDF) directly causes threshold voltage to vary randomly from device to device: a channel that happens to contain slightly more dopant atoms than its neighbor has a measurably different threshold voltage, purely from this atomic-scale randomness, not from any process equipment imperfection.

RDF's impact grows as devices shrink, precisely because a smaller channel contains fewer total dopant atoms, so the same absolute atom-to-atom count variation represents a larger fractional variation. This is one of several reasons advanced nodes have moved toward lower channel doping and multi-gate structures (lesson 5) that rely less on channel doping to set threshold voltage in the first place, reducing RDF's impact by reducing how much the result depends on exactly how many dopant atoms happen to be present.

8.2 Line-edge roughness and work-function variation

Two further variability sources, both tied to process steps covered elsewhere in this section:

• Line-edge roughness (LER): a patterned edge (for example, a gate's edge, defined by the lithography and etch steps this section's Lithography, Etch & CMP path covers) is never perfectly smooth at the atomic scale; it has some roughness, a small random deviation from the intended straight edge. For a gate, LER translates directly into a randomly varying effective channel length from one point along the gate's width to another, and channel-length variation feeds directly into the short-channel effects lesson 4 described, adding yet another source of device-to-device (and even within-device) Vt variation.
• Work-function variation (WFV): in a metal-gate device, the gate's work function (an intrinsic material property that helps set threshold voltage) depends on the specific crystal grain orientation of the metal at each point along the gate, since different grain orientations of the same metal can have measurably different work functions. Because grain orientation itself varies randomly from grain to grain, and a very small gate may contain only a few grains, WFV is another random, atomic/microstructure-scale contributor to Vt variation, and like RDF, its relative impact grows as gates shrink and each one spans fewer grains.

8.3 Reliability: BTI, HCI and TDDB

Variability (8.1-8.2) describes differences present from manufacture; reliability covers how a device's characteristics shift during its operating lifetime, under normal electrical stress. Three mechanisms are commonly characterized at the device level:

• Bias temperature instability (BTI): sustained gate bias (negative for a PMOS device, NBTI; positive for an NMOS device, PBTI) at elevated temperature generates and traps charge at or near the gate-oxide interface over time, gradually shifting threshold voltage. BTI is partly recoverable (some trapped charge relaxes when the stress bias is removed) and partly permanent, and its magnitude depends on the fraction of time a device spends under stress bias, which is why a design's duty cycle, not just its peak voltage, matters for BTI-aware aging margins.
• Hot-carrier injection (HCI): carriers accelerated by a high lateral electric field (commonly near the drain, where lesson 4's short-channel field concentration is highest) can gain enough energy to be injected into the gate oxide, where they become trapped and permanently degrade device characteristics (shifting Vt, reducing drive current) in a way that does not recover. HCI is specifically tied to switching activity (it needs a field high enough to accelerate carriers, present mainly during transitions) rather than static bias, distinguishing it from BTI's duty-cycle dependence.
• Time-dependent dielectric breakdown (TDDB): the gate oxide, stressed by the electric field across it over the device's operating lifetime, accumulates defects over time until a conductive path eventually forms through it, a catastrophic, not gradual, failure. TDDB is modeled statistically (a population of nominally identical devices fails at a distribution of times, not all at once), and defines a maximum allowed operating voltage and oxide thickness combination for a target lifetime (commonly specified as a target failure rate after a defined number of years of operation).

All three mechanisms are why a signoff timing margin includes an aging guard-band, covered in this site's STA material: a chip's timing has to close not only at time zero, but after years of BTI- and HCI-driven degradation, and TDDB sets an outright voltage ceiling the design must never exceed for its target lifetime.

8.4 Interview questions

What is random dopant fluctuation, and why does its impact grow as devices shrink? The random atom-to-atom variation in how many dopant atoms, and where, actually land in a given channel, causing random Vt variation between nominally identical devices; its relative impact grows because a smaller channel contains fewer total dopant atoms, so the same absolute count variation is a larger fraction of the total.

How does line-edge roughness cause Vt variation? A patterned gate edge is not perfectly smooth; the resulting random variation in effective channel length along the gate's width feeds into the same short-channel effects that channel length itself controls, varying Vt.

What causes work-function variation in a metal-gate device? Different crystal grain orientations of the gate metal have different work functions; since grain orientation varies randomly and a small gate may span only a few grains, this randomly varies local threshold voltage.

Distinguish BTI and HCI as reliability mechanisms. BTI is driven by sustained gate bias at elevated temperature and depends on duty cycle (time under stress), partly recoverable; HCI is driven by a high lateral field (mainly near the drain, during switching) accelerating carriers into the gate oxide, and is not recoverable.

What does TDDB set a limit on, and why is it modeled statistically? It sets a maximum operating voltage and oxide thickness combination for a target device lifetime; it is modeled statistically because a population of nominally identical devices fails at a distribution of times under the same stress, not simultaneously, so a target failure rate over a defined lifetime is specified rather than a single deterministic failure time.