Fab Economics and Careers

Every lesson in this path has built toward one idea: yield is not an abstract quality metric, it is the direct link between the physics and process control covered across this whole section and a fab's actual business outcome. This closing lesson makes that link explicit with two standard formulas, dies per wafer and cost per good die, and then turns to where a career in this field actually sits, the roles across fab and OSAT (assembly, packaging and test) manufacturing.

Reading time: about 8 minutes.

10.1 Dies per wafer

Before yield is even applied, the number of dies that geometrically fit on a wafer is itself a function of die size and wafer diameter. A simplified, commonly used approximation is:

Dies per wafer ~ (pi * (D/2)^2) / die_area - (pi * D) / sqrt(2 * die_area)

where D is wafer diameter and die_area is the area of one die. The first term is simply the wafer's circular area divided by die area, the maximum number of dies that could fit if the wafer were a perfect rectangle with no wasted area; the second, subtracted term corrects for edge loss, the dies that would geometrically overlap the wafer's curved boundary and therefore cannot actually be printed as complete, usable dies there. This formula is an approximation, not an exact geometric count (the exact count depends on the specific die aspect ratio and exactly how dies are arranged on the reticle grid relative to the wafer's center), but it captures the two first-order effects correctly: more dies fit on a larger wafer, and a larger die area always reduces dies-per-wafer, both before any yield loss is even applied.

10.2 Cost per good die

Combining dies-per-wafer with yield (lesson 7) gives the number of good dies a wafer actually produces, and dividing total wafer processing cost by that number gives cost per good die:

Good dies per wafer = Dies per wafer * Y
Cost per good die = Wafer cost / Good dies per wafer

This is the formula that makes yield a direct line item, not just a quality metric: at a fixed wafer cost and a fixed die size, a lower yield directly raises cost per good die, proportionally to how much yield has fallen, because the fixed cost of processing that wafer is now spread across fewer good dies. This is also why a larger die, which lesson 7's Poisson model already showed yields worse at a fixed defect density, is doubly expensive, fewer dies fit on the wafer to begin with (10.1), and a larger fraction of those are bad (lesson 7), compounding into cost per good die rising faster than die area alone would suggest.

10.3 What drives wafer cost

Wafer cost itself is driven by several factors covered across this whole section: the number and complexity of process steps in the route (lesson 1.3), with more layers and more advanced lithography, including EUV layers (Lithography, Etch & CMP lesson 5), directly adding processing cost and cycle time; equipment depreciation, especially for the most capital-intensive tools (lesson 4's scanners above all); materials and consumables (photoresist, slurry, process gases); and fab operating costs, including the cleanroom infrastructure itself (lesson 1.1) and the labor, both direct process operators and the process, equipment and yield engineers whose work this whole path has covered. A technology node's cost roadmap is, in large part, a running tally of how these factors trade off against the density and performance gains each new node delivers, which is exactly why DTCO (covered in the Device & TCAD path's closing lesson) increasingly treats area, cost and yield together, rather than optimizing device performance in isolation from what it costs to actually manufacture.

10.4 Roles in fab and OSAT manufacturing

This whole section's scope, from lithography physics to device structure to fab operations and yield, corresponds to a real range of manufacturing career roles:

• Process engineers, specializing in a specific process module (litho, etch, deposition, CMP, implant, thermal) the way this section's Lithography, Etch & CMP path and this path's lessons 2-3 both covered module by module.
• Device and TCAD engineers, the dedicated role covered in depth in the Device & TCAD path.
• Equipment engineers, responsible for a specific tool type's uptime, maintenance and qualification, directly tied to this lesson's earlier coverage of OEE and chamber matching.
• Process integration engineers, coordinating how individual process modules fit together into a working, qualified full flow.
• Yield engineers, specializing in exactly the statistical and physical analysis lessons 7-8 covered.
• Test and product engineers, working at the OSAT (assembly, packaging and test) side, covered only briefly in this path but central to getting a good die from wafer to a shipped, packaged, tested part.

In India, this field is comparatively new, growing with projects creating jobs that did not exist here a few years ago; examples include the Tata Electronics fab at Dholera and ATMP and OSAT units at Sanand and in Assam. Many of these roles are open to diploma holders and to B.Tech graduates in electrical, chemical, mechanical and materials engineering, a notably broader entry path than the electronics-specific degrees most front-end design roles on this site's other career pages expect, reflecting manufacturing's genuinely interdisciplinary nature, process control, statistics, equipment, materials science and electrical fundamentals all playing a real role.

10.5 Interview questions

What two effects does the dies-per-wafer formula's edge-loss term account for? Dies that would geometrically overlap the wafer's curved edge and therefore cannot be printed as complete, usable dies; the formula's first term (circular area divided by die area) overstates the count without this correction.

Why does a larger die cost disproportionately more per good die, not just proportionally more? A larger die both reduces dies-per-wafer (fewer fit geometrically) and yields worse at a fixed defect density (lesson 7's exponential Poisson relationship), so both effects compound together rather than just one scaling cost.

Name three factors that drive wafer processing cost. Any three of: number and complexity of process steps (including EUV layer count), equipment depreciation (especially the most capital-intensive tools), materials and consumables, and fab operating/labor costs.

What is the difference between a process engineer and an equipment engineer, broadly? A process engineer specializes in a specific process module's recipe and results (litho, etch, deposition, etc.); an equipment engineer is responsible for a specific tool type's uptime, maintenance and qualification, a more hardware-focused role.

Why are many Indian fab and OSAT roles open to a broader range of degrees than front-end design roles typically are? Manufacturing work spans process control, statistics, equipment and materials science alongside electrical fundamentals, a genuinely interdisciplinary mix that fits graduates from electrical, chemical, mechanical and materials engineering, as well as diploma holders, not only electronics-specific degrees.