How a Chip Is Patterned | Lithography, Etch & CMP

A finished chip is not built in one pass. It is built as a stack of layers, each one patterned, and the pattern on every layer has to line up with the pattern on the layer below it to within a fraction of the smallest feature on the chip. This path is about how that patterning actually happens: the chemistry and optics of lithography, the physics of etch, and the mechanical polishing step, chemical-mechanical planarization (CMP), that makes the next layer possible.

This first lesson sets the map. It names the three zones of a finished chip, front-end-of-line (FEOL), middle-of-line (MEOL) and back-end-of-line (BEOL), and it introduces the loop of process steps that repeats, with small variations, for nearly every one of the dozens of layers between them.

Reading time: about 8 minutes.

1.1 Three zones: FEOL, MEOL, BEOL

A modern logic chip is commonly described in three zones, stacked bottom to top:

FEOL (front-end-of-line). Everything built into or directly on the silicon substrate: well formation, shallow trench isolation, the transistor's gate stack, and source/drain formation. FEOL is where the transistor itself is made.
MEOL (middle-of-line). The contacts that connect the transistor's gate, source and drain terminals up to the first wiring layer. This zone is short, often just one or two contact layers, but it is extremely dense and exacting, because it is the narrowest bottleneck between the device and the wires above it.
BEOL (back-end-of-line). The interconnect stack: many layers of metal wiring and the vias that connect one metal layer to the next, from the lowest, finest-pitch metal up to the thick top-level power and I/O routing.

A leading-edge logic process might have on the order of fifteen to twenty metal layers in BEOL alone, on top of the FEOL and MEOL layers. Lessons 1-2 of the physical design path already covered what each layer is for, from the design side: floorplanning, placement and routing all assume this stack exists. This path covers how each layer is actually manufactured.

The three zones of a finished chip. FEOL builds the transistor into the silicon; MEOL is a thin, dense contact zone; BEOL is many metal and via layers, from the finest pitch near the device up to thick top-level routing and the bond pad.

1.2 The per-layer loop

Every layer in this stack, whether it is a FEOL implant mask, a MEOL contact, or a BEOL metal line, is made by a version of the same six-step loop:

Deposit (or grow) a film of the material the layer needs: an oxide, a metal, a nitride, polysilicon.
Litho: coat the wafer with photoresist, expose it through a mask so the resist pattern matches the design intent for that layer, and develop away the exposed (or unexposed) resist. Lessons 2-6 of this path cover litho in depth.
Etch: remove the film wherever the resist does not protect it, transferring the resist pattern into the film below. Lessons 7-8 cover etch.
Strip: remove the now-used resist.
Clean: remove particles and residues left by etch and strip, so the next deposition starts on a clean surface.
CMP (not every layer): planarize the wafer so the next layer's litho has a flat surface to focus on. Lesson 9 covers CMP.

Not every layer uses every step in this exact order; an implant layer, for example, replaces "deposit" with an ion implant step, and not all layers need CMP. But the deposit-pattern-etch-clean rhythm, repeated with small variations, is the backbone of the whole process, and it is worth holding in mind through every later lesson in this path: each lesson is really drilling into one or two steps of this same loop.

The per-layer loop. Most layers run deposit, litho, etch, strip and clean; some layers also need CMP before the loop starts again for the next layer up the stack.

Not every layer runs the loop identically; an implant layer, for example, substitutes an ion implant step for "deposit" (a dopant is introduced into existing silicon rather than a new film being deposited on top of it), and a layer that only needs to remove material without adding anything first, like a trench etch directly into the substrate, can skip the deposit step entirely for that particular layer. The loop as drawn is the common pattern most layers follow, not a rigid, unvarying sequence every single layer obeys without exception.

1.3 Worked example: one metal layer, start to finish

Worked example: patterning one copper damascene metal layer

Assumptions: a single-damascene copper metal layer, the common BEOL scheme at most nodes.

Deposit an inter-layer dielectric (ILD) oxide over the previous layer.
Litho: coat resist, expose the trench pattern for this metal layer, develop.
Etch the trenches into the ILD where the resist is open.
Strip the resist, then clean the wafer.
Deposit a thin barrier/liner, then deposit copper to overfill the trenches (lesson 9 covers copper CMP in depth).
CMP removes the overburden copper and barrier down to the ILD surface, leaving copper only in the trenches and a flat, clean surface for the next layer's litho.

Notice that this is "damascene" precisely because the metal is inlaid into trenches cut in the dielectric, rather than deposited as a blanket film and etched into lines; copper is hard to etch cleanly, so the industry patterns the dielectric instead and polishes the copper back with CMP.

1.4 Interview questions

What are FEOL, MEOL and BEOL, in one sentence each? FEOL builds the transistor into the silicon; MEOL is the thin, dense contact zone connecting the transistor to the first wiring; BEOL is the many-layer metal and via interconnect stack above MEOL.

Name the six steps of the per-layer loop in order. Deposit, litho, etch, strip, clean, and (for some layers) CMP.

Why does a copper metal layer use damascene patterning instead of depositing and etching copper directly? Copper is difficult to etch with the volatile-byproduct chemistries etch normally relies on, so the dielectric is patterned with trenches instead, copper is deposited to overfill them, and CMP polishes the excess back, leaving copper only where the trenches are.

Why does a layer need CMP before the next layer's lithography? Lithography has a limited depth of focus; a non-flat surface left by deposition over an already-patterned layer would put parts of the next layer's features out of focus. Lesson 3 covers depth of focus directly.

Which zone is denser, MEOL or the top metal layers of BEOL, and why? MEOL is denser. Feature size and pitch generally grow going up the BEOL stack, from the finest pitch near the device to much coarser, thicker top-level routing, so the layers nearest the transistor are the tightest.

Key takeaways

A finished chip is FEOL (the transistor), MEOL (thin contact zone) and BEOL (many metal/via layers), stacked from the substrate up.
Nearly every layer is built with the same loop: deposit, litho, etch, strip, clean, and sometimes CMP.
Copper BEOL layers use damascene patterning: the dielectric is patterned with trenches, and CMP polishes back copper deposited to overfill them.
Feature size generally grows going up the stack, from the densest layers near the substrate to coarser top-level routing.
Every later lesson in this path is really a deeper look at one or two steps of this same per-layer loop.