Design rule constraints

Timing constraints say how fast the design must be. Design rule constraints (DRCs) say how safe each net must be. A net that violates them might still meet timing on paper but can be unreliable in silicon. This lesson covers the three common limits and how the tool treats them.

Reading time: about 6 minutes.

7.1 The three limits

• Maximum transition – the longest allowed rise or fall time on a net. A slow edge makes the next cell slow, raises short-circuit power, and makes noise more harmful.
• Maximum fanout – the largest number of input pins one driver may feed. High fanout implies a large load and a slow edge.
• Maximum capacitance – the largest total load a driver pin may see. Each output pin in the library has its own limit, because a small cell cannot drive a large load cleanly.

All three are really about the same physical thing, a driver asked to charge more capacitance than it was designed for.

7.2 Where the limits come from

Limits arrive from two places.

1. The library – the Liberty file states a maximum capacitance and a maximum transition for most pins. The tool respects these without being told.
2. The designer – tighter limits can be added through constraints.

Because the library limits are always active, a design with no DRC constraints at all is still checked against them. The designer's value is always an additional restriction, never a relaxation. If the designer's limit is looser than the library's, the tighter one typically applies.

7.3 Setting them

In SDC form, which is portable across tools:

set_max_transition 0.30 [current_design]
set_max_fanout 16 [current_design]
set_max_capacitance 0.10 [all_outputs]

Genus also accepts these as attributes on the design or a port, using its native set_db form with an object and a value, for example set_db <design_or_port> .max_transition 0.30. Both forms do the same job. It is better to use the SDC form in the main constraint file, because the same file can then be reused by other tools in the flow.

In SDC commands, time is in ns and capacitance in pF (see the unit trap in Lesson 2). Check the unit declaration at the top of the library if in doubt, and confirm that a transition value such as 0.30 means ns in your version.

7.4 Why DRCs rank above timing

Suppose a net has a fanout of 80 and meets its timing target by a small margin. A tool that respects DRCs first will split it with buffers, even though the timing was fine. This is intentional. A violating net is not guaranteed to behave as the library predicts, because the delay tables only cover the slew and load ranges that were characterized. Outside that range the numbers are extrapolated.

Thus, the order of priority is typically: meet DRCs, then meet timing, then reduce area and power. If you see the tool adding buffers where timing was already met, a DRC is usually the reason.

7.5 Ideal networks and exemptions

Some nets are deliberately exempt. The clock network and the asynchronous set and reset networks are treated as ideal, which means the tool will not apply DRCs to them or buffer them. They have thousands of fanouts by design, and the next steps in the flow, clock tree synthesis and reset buffering, handle them properly.

# Example for a buffered net in a larger design; acc8 does not need it
set_db pin:<design>/<buf_inst>/Z .ideal_network true

This is useful when an enable or reset signal fans out to a large number of registers and a later tool is going to build the tree. Used carelessly, it hides a real problem. Always write down which nets were declared ideal and why.

7.6 Wire load models

Before placement, the tool does not know how long a wire will be. Older flows use a wire load model that estimates wire capacitance from the fanout of a net. Genus allows a specific model to be forced on a design:

set_db <design> .force_wireload 1x1

Newer flows rely on physical information instead, reading floorplan data so wire lengths are estimated from placement. Which one applies depends on the technology node and the flow. In advanced nodes, wire load models are usually too crude, and physical-aware synthesis is the norm. State in your project notes which approach your flow uses.

7.7 Reading the violations

After synthesis, ask for the design rule report. The exact command name depends on the tool version, so use the built-in help to find the report command for design rule violations. In general, the report lists each violating net, the limit, the actual value and the amount of violation. A clean run should list no violations, or only ones on nets that were declared ideal.

7.8 Why an interviewer asks about this

DRCs are a quick way to see whether a candidate understands the difference between a timing problem and an electrical problem. Likely questions: "what is max transition and why does it matter", "why does the tool buffer a net that already meets timing", and "why is the clock exempt". The expected reasoning is that library tables are only valid inside their characterized range.