Handing off to place and route

Synthesis is finished when someone else can use its result without asking questions. That means the netlist, the constraints, the reports and the script that produced them are saved together and checked. This lesson covers the write commands and ends with a complete script that ties the path together.

Reading time: about 6 minutes.

11.1 Writing the netlist

write_hdl > acc8_netlist.v

The redirection character matters: without > the netlist prints to the screen. If the command is run before mapping, the netlist written is a generic one, since a mapped netlist does not exist yet. For a hand-off, always run it after syn_map or syn_opt.

Variations:

# One named design (its sub-hierarchy is written with it)
write_hdl /designs/acc8/ > acc8_only.v

# Each primitive written as a simple assign expression
write_hdl -equation > acc8_eq.v

# A technology-independent netlist, useful for debug
write_hdl -generic > acc8_generic.v

A generic netlist is helpful for looking at structure, but a downstream tool must receive the technology-mapped one. If the netlist will be used in a third-party tool, write the mapped gate-level version.

11.2 Writing the constraints

write_sdc > acc8_out.sdc

Write the constraints from the synthesis session even if the original SDC file is still available. The written file reflects what the tool actually applied, including any change made interactively and any constraint that was dropped. It is the one the next tool should read. Comparing it with the input file is a quick audit: lines that vanished deserve an explanation.

11.3 Writing delays

write_sdf > acc8.sdf

An SDF file holds the delay of every cell and interconnect arc, and is used for gate-level simulation with timing annotation. It is written right after synthesis. Remember that this is a synthesis-time estimate. Wire delays are approximate, so an SDF from this stage is useful for early checks and not for sign-off.

11.4 Saving the session

write_db -to_file acc8_syn.db
write_script > acc8_session.tcl

write_db saves the design database so the session can be restored without re-running synthesis. write_script writes out the commands that recreate the constraints and settings. Together they let a colleague, or you in a month, reproduce the state exactly. Keep these with the netlist.

11.5 What the next tool will care about

Before handing off, check these items.

1. Hierarchy – is the hierarchy the one the floorplan expects? A netlist that was flattened will not match a hierarchical floorplan.
2. Names – are instance and net names legal in the next tool? Characters such as backslashes and brackets in names sometimes need escaping, and naming style attributes can control this.
3. Unmapped or generic cells – none should remain. A search for generic cell names in the netlist is a cheap check.
4. Constraints – read the written SDC in a timing tool or a fresh session and see that it loads with no errors.
5. Scan and test – if scan chains were inserted, the chain information is required by placement. Make sure it is also written out.
6. Equivalence – if formal verification is part of the flow, run it between RTL and the netlist now, not after place and route.

Thus, the check on the written files is the real finish line of synthesis, and it takes minutes compared to the hours lost when a bad hand-off is found later.

11.6 A complete template

The following script ties the whole path together. It is the same sequence we met one lesson at a time.

# ---- environment -------------------------------------------------
set_db init_lib_search_path  /path/to/libs
set_db init_hdl_search_path  ./rtl
set_db script_search_path    ./scripts
set_db library               typical.lib

# ---- design ------------------------------------------------------
read_hdl -language v2001 acc8.v
elaborate acc8

# ---- constraints (units: ns, pF) ---------------------------------
read_sdc acc8.sdc
report_timing -lint

# ---- options -----------------------------------------------------
set_db syn_generic_effort medium
set_db syn_map_effort     medium
set_db syn_opt_effort     medium

# ---- synthesis ---------------------------------------------------
syn_generic
syn_map
syn_opt

# ---- reports -----------------------------------------------------
report_timing -lint  > lint.rpt
report_timing        > timing.rpt
report_area          > area.rpt
report_gates         > gates.rpt

# ---- hand-off ----------------------------------------------------
write_hdl     > acc8_netlist.v
write_sdc     > acc8_out.sdc
write_sdf     > acc8.sdf
write_db -to_file acc8_syn.db
write_script  > acc8_session.tcl
quit

Every line maps to a lesson: environment (2), design (3), constraints (4 to 7), synthesis (8), reports (9), hand-off (11). Once the structure is clear, it is easy to adapt to a different design.

11.7 Where to go next

This path covered the flow from one library and one mode. Real projects add several corners and modes, scan insertion, physical-aware synthesis, low-power intent, and formal checks. Each builds on exactly the steps above. The next topics in the Back-End section, floorplanning, placement and clock tree synthesis, start from the netlist and SDC you just learned to write.

11.8 Why an interviewer asks about this

"What do you hand over after synthesis?" is a common question, because the weak answer is "the netlist". The strong answer lists the netlist, the written SDC, the reports, the script and the verification status, and explains why each is needed. Expect follow-ups about hierarchy preservation and equivalence checking.