Reading and elaborating RTL

Loading a design into the tool takes two steps, and they are not the same. Reading checks the syntax and stores the code. Elaboration builds the actual design for a chosen top module and resolves its parameters. Many beginner problems come from not knowing which of the two failed.

Reading time: about 6 minutes.

3.1 Reading the files

The command that loads source files is read_hdl.

read_hdl [-language {v1995 | v2001 | sv | vhdl}]
         [-define name[=value]]
         [-library name]
         [-netlist]
         files

A basic call for our accumulator is:

read_hdl -language v2001 acc8.v

More than one file can be given in a list, or as several calls:

read_hdl {top.v block1.v block2.v}

The order of files often does not matter for plain Verilog, except where a file defines a macro that another file uses. Package files in SystemVerilog and VHDL must be read before the files that use them. A file that has been read is not yet a design. It is only a set of modules waiting to be chosen.

3.2 Choosing the language

If -language is omitted, the tool typically decides from the file extension or from a default setting. That default may differ between installations, so it is better to state the language explicitly in the script. A mismatch is a common reason why a valid SystemVerilog construct gives a syntax error: the file was read as Verilog 2001.

read_hdl -language sv my_block.sv
read_hdl -language vhdl -library work top.vhd

VHDL files can be assigned to a named library with -library, and the same name must be used when the design is referred to later.

3.3 Defines

Preprocessor macros can be set from the command line, the same way -D works for a simulator.

read_hdl -define WIDTH=16 -define USE_FAST_ADDER top.v

This is useful when one RTL tree serves several configurations. The risk is that the define is easy to forget when the script is edited. A synthesis log that reads clean can still describe the wrong configuration, so print the defines in the log by echoing them from the script.

3.4 Elaboration

elaborate takes the name of the top module and builds the design.

elaborate acc8

During elaboration the tool:

• resolves parameters and generates the right structure for each;
• creates a separate module for each unique parameter set, so two instances of the same module with different widths become two different modules;
• connects hierarchy and reports unresolved references, which means an instance whose module definition was never read.

Parameters can be overridden at this point instead of editing the RTL:

elaborate alu -parameters {{WIDTH 16} {DEPTH 8}}

Thus, -define changes how the text is read, and -parameters changes how the design is built. They look similar but act at different times.

3.5 What the log tells you

After elaboration, read three things in the log.

1. Unresolved references – a module that was instantiated but not found. This is usually a file that was not read.
2. Latch inference – the tool tells you when a combinational block does not assign every output on every path, which creates a latch. If you did not intend a latch, the RTL needs a default assignment.
3. Unused or undriven signals – these often point to a typo in a signal name.

The report_messages command prints a summary of the messages issued during the session. It is the fastest way to see whether a run was clean.

3.6 Reading a netlist instead of RTL

The same command also reads a gate-level netlist, for example one from an earlier run or a hard IP block.

read_hdl -netlist block_netlist.v

Without -netlist, the file is treated as RTL. With it, the instances are matched to library cells. Mixing the two up gives confusing errors, such as cell names being reported as unresolved modules.

3.7 Hierarchy and what the tool keeps

By default the tool may ungroup parts of the hierarchy during optimization, mostly at high effort, so it can optimize across boundaries. This usually gives smaller results. However, if the design will later go through formal equivalence checking or hierarchical place and route, the structure often needs to be preserved. We look at this in Lesson 10. For now, the point is that elaboration only builds the hierarchy. It is the later optimization step that decides whether to merge it.

3.8 Why an interviewer asks about this

Questions here test whether a candidate has actually run a tool. "What does elaboration do?" separates people who have read about synthesis from people who have debugged it. A strong answer mentions parameter resolution and unique module creation. Also expect a question on latch inference, which is both an RTL-coding topic and a synthesis-log topic.