Foundations path

Verilog

A free, 14-lesson beginner path to writing synthesizable RTL: modules, combinational and sequential logic, FSMs, testbenches, and a close look at SystemVerilog.

14
lessons
Beginner
level
Free
every lesson
Start with lesson 1 →

Verilog

  1. 1What Verilog Really IsWhy hardware needs its own kind of language, how the same code means two things to a simulator and a synthesis tool, and the flow that turns it into silicon.
  2. 2Your First ModuleThe module/endmodule skeleton, ANSI-style ports, how an instance differs from a module definition, and a half adder that actually compiles and runs.
  3. 3Wires, Regs, and the Four ValuesWhy Verilog has two kinds of signal instead of one, the 0/1/x/z value set every signal actually carries, and bit and part selects on a vector.
  4. 4Operators You Will Actually UseBitwise versus logical operators, shifts, concatenation and replication, the conditional operator, and two width and sign pitfalls that pass simulation silently.
  5. 5Combinational Logicassign versus always @*, a 4-to-1 multiplexer built both ways, and a real simulated demonstration of the classic incomplete-sensitivity-list bug.
  6. 6If, Case, and Avoiding LatchesHow a missing branch gets you an unwanted latch instead of a mux, confirmed by real synthesis output, plus the casez/casex hazards that catch the pattern's own fix.
  7. 7Sequential Logic and the ClockThe standard flip-flop template, synchronous versus asynchronous reset proven in simulation, an enabled counter, and why reg doesn't always mean a real flip-flop.
  8. 8Blocking vs Non-BlockingWhat = and <= actually schedule inside a simulator, a 3-stage pipeline that silently collapses to one register when coded wrong, and the guidelines that prevent it.
  9. 9Finite State MachinesThe three-process FSM coding style, why it keeps clocked and combinational logic separate, and a working 1011 detector verified against two overlapping matches.
  10. 10Writing a TestbenchTasks, self-checking PASS/FAIL output built on the === operator, a deliberately broken test that proves the checker works, and dumping a waveform to a viewer.
  11. 11Synthesizable RTL and Next StepsWhat a synthesis tool actually does with a delay or an initial block, confirmed by real Yosys runs, a full coding checklist, and what to learn next.
  12. 12Parameters and GenerateMaking one module work at any width with parameter, replicating hardware with a generate loop, and sizing a vector automatically with $clog2.
  13. 13Common RTL Building BlocksAn edge detector, a synchronizer, a register file, a small ALU, and a synchronous FIFO -- five blocks common in real RTL, each verified against a real testbench.
  14. 14From Verilog to SystemVeriloglogic, always_comb/always_ff catching a real latch bug as a build error, enum and .* port connections, and what to learn next.