UPF Power Intent, Isolation Cells, and Level Shifters: Low Power Guide
Battery-powered mobile SoCs, high-performance computing, and automotive silicon require aggressive low-power design techniques: multiple voltage domains, power gating (MTCMOS), state retention, and IEEE 1801 Unified Power Format (UPF). This guide breaks down the physical implementation and verification rules.
1. Power Domains & Voltage Areas
A Power Domain is a logical collection of design modules that share a common primary power supply net and ground supply net. In physical layout, each power domain maps to a physical Voltage Area on the die.
create_power_domain PD_TOP
create_power_domain PD_CPU -elements {u_cpu_core}
2. Isolation Cell Strategy & Clamping Rules
When a power-gated domain powers off, its output nodes become floating (high-impedance Z). If these floating lines drive standard CMOS gates in a constantly powered active domain, both NMOS and PMOS transistors in the receiver turn partially ON simultaneously, resulting in continuous crowbar shoot-through current from VDD to VSS that drains the battery and can cause physical burnout.
Isolation cells clamp the floating signal to a known legal logic state (0 or 1) using an active isolation enable control signal from a power management controller:
-domain PD_CPU \
-isolation_power_net VDD_ALWAYS_ON \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
3. Level Shifter Architecture & Voltage Crossings
When signals travel across domains operating at different supply voltages, level shifters must be inserted:
- Low-to-High Level Shifter (e.g. 0.7V → 1.0V): Mandatory. Without it, a 0.7V logic 1 cannot turn off the PMOS transistor in a 1.0V standard cell, causing continuous leakage current and degraded rise times.
- High-to-Low Level Shifter (e.g. 1.0V → 0.7V): Often optional for function in some libraries, but recommended for timing and oxide reliability to prevent overstressing thin-gate oxide devices.
4. State Retention & Always-On Power Networks
When a CPU or GPU core enters power-gated sleep, saving its internal architectural register state to external DRAM takes thousands of clock cycles and wastes energy. Retention registers contain an always-on shadow latch powered by a backup supply (VDD_AON) that preserves register contents during sleep and restores them within a single clock cycle upon wake-up.
→ Practice Full Q&A: Retention register operation and save/restore sequencing6. Power State Tables (PST) & Signoff Checks
Why are isolation cells mandatory when a power domain is switched off?
When a domain shuts down, its output pins float to undefined intermediate voltage levels. Without isolation cells clamping the signal to a clean logic 0 or 1, downstream receiving gates in active domains experience massive crowbar shoot-through currents or functional corruption.
When is a level shifter required vs an isolation cell?
A level shifter is required when a signal crosses between two domains operating at different voltage levels (e.g. 0.7V to 1.0V) to prevent threshold leakage and propagation delay degradation. An isolation cell is required when the transmitting domain can power off while the receiving domain remains powered.
What is an Enable Level Shifter (ELS)?
An Enable Level Shifter combines voltage translation and isolation clamping logic into a single standard cell, saving area and routing congestion on domain boundaries.