What are the three components of dynamic power dissipation in a CMOS gate?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
A CMOS gate's power breaks down into three pieces: a leakage component (subthreshold conduction, gate-oxide tunneling, and reverse-biased junction leakage), an internal/short-circuit switching component (crowbar current when both pull-up and pull-down paths are briefly on together during a transition), and an output-charging component (the classic charging and discharging of the load capacitance).
Mentor Explanation
A beginner often assumes power dissipation is just 'charging the capacitor,' but a worked NAND example shows there's more going on during a transition than that. Think of it this way: while the input is slewing through the region where both PMOS and NMOS are partially on, a brief current path forms straight from supply to ground — that crowbar current is wasted power that never touches the output load.
Example
In a worked NAND gate example, the total dynamic power came out to 35.6 uW once all three components — leakage, internal switching, and output charging — were added together.
Why It Matters
Recognizing all three matters for accurate power estimation and for choosing the right implementation fix — for instance, a slow input slew rate specifically worsens the internal shortcircuit component, which is why slew-rate control is part of a low-power flow.
Equation
Output charging power = C * Vdd^2 * fCommon Beginner Mistake
A common mistake is to only model the output-charging term (C·Vdd²·f) and ignore short-circuit/crowbar current, which can meaningfully understate a gate's real dynamic power, especially with slow input transitions.
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