Level 1 · Foundations

Beginner Low Power Interview Questions

Build a clear foundation in power components, domains, supplies, isolation, level shifting, retention, switches, and UPF.

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Build a clear foundation in power components, domains, supplies, isolation, level shifting, retention, switches, and UPF.

  1. 01 Why is low-power design necessary in modern chip design?Beginner · Low-power design is the discipline of deliberately controlling how much energy and current a chip draws, because as process nodes have shrunk, both the active (switching) power and the standby leakage power of a chip have grown to the point where they now limit what a design can do.
  2. 02 What is the difference between dynamic power and leakage (static) power?Beginner · Dynamic power is the power consumed only when circuits are actively switching (charging/ discharging capacitance, and momentary short-circuit current), while leakage (static) power is the power a circuit consumes even when it is not switching at all, simply because transistors are never perfect off-switches.
  3. 03 What are the three components of dynamic power dissipation in a CMOS gate?Beginner · A CMOS gate's power breaks down into three pieces: a leakage component (subthreshold conduction, gate-oxide tunneling, and reverse-biased junction leakage), an internal/short-circuit switching component (crowbar current when both pull-up and pull-down paths are briefly on together during a transition), and an output-charging component (the classic charging and discharging of the load capacitance).
  4. 04 What causes leakage power in a CMOS transistor?Beginner · Leakage power in a CMOS transistor comes from current that flows even when the transistor is nominally 'off' — this comes from subthreshold conduction, gate-oxide tunneling current, and reverse-biased junction leakage.
  5. 05 What is the trade-off between high-threshold-voltage (HVt) and lowthreshold-voltage (LVt) cells?Beginner · HVt cells have a higher threshold voltage, which gives them lower leakage power and lower dynamic power but a larger delay (slower switching); LVt cells have a lower threshold voltage, giving faster switching (smaller delay) at the cost of significantly higher leakage power.
  6. 06 How does temperature affect leakage power?Beginner · Leakage power is temperature-dependent — this dependence is well characterized in device data, and it is exactly why the industry-standard worst-case power signoff corner is defined at maximum operating temperature, alongside fast process and maximum voltage.
  7. 07 How does process corner (fast/typical/slow) affect power?Beginner · Process corner describes where on the fast-to-slow manufacturing spectrum a given chip landed, and characterization data shows that a 'fast' wafer corner delivers much better timing performance but is the corner that barely meets the power spec, while a 'slow' corner has much lower leakage and active power than spec (at the cost of barely passing timing).
  8. 08 What is the "worst-case power corner" used for power signoff?Beginner · The worst-case power corner is the PVT (process, voltage, temperature) combination defined as fast process, maximum voltage, and maximum temperature — the combination that produces the highest leakage and dynamic power a design could realistically see.
  9. 09 Why does reducing supply voltage (Vdd) help reduce power, and what is the trade-off?Beginner · Reducing supply voltage reduces power because power is a function of the square of the voltage — so even a modest voltage cut yields a much larger power reduction — but the trade-off is reduced circuit speed, since lower voltage means slower switching and less margin against process/temperature variation.
  10. 10 What is a power domain?Beginner · A power domain is a grouping of design blocks that share one common power supply — blocks sharing one common power supply — and every power domain must have exactly one primary power net and one primary ground net.
  11. 11 Can you give an example of a chip with multiple power domains?Beginner · A classic multi-voltage example is a top-level domain running at 1.0V that contains three subblocks each running at a different fixed voltage: an ARM926 processor at 1.2V, a DMA block at 1.1V, and an APB peripheral block at 0.9V.
  12. 12 What are the different states a power domain can be in (fixed voltage, switchable, DVS, DFS, DVFS)?Beginner · A power domain can be operated at a static fixed voltage (simply set once for its function), can be switchable (fully powered on or off via power gating), can use variable frequency / DFS (dropping clock frequency, or shutting clocks off entirely, in idle mode), can use DVS (dynamically adjusting only voltage based on measured speed/performance needs), or can use full DVFS (dynamically adapting both voltage and frequency together via look-up tables or on-chip monitors).
  13. 13 What are supply nets and supply ports in UPF?Beginner · A supply net in UPF is a conductor that carries a supply voltage or ground reference to a power domain (created with create_supply_net), while a supply port is the UPF-level connection point (created with create_supply_port) used to bring a supply net into or out of a hierarchical scope; connect_supply_net then wires a net to a list of ports.
  14. 14 What is a supply set in UPF?Beginner · A supply set is an abstract, domain-independent collection of supply nets grouped around two functions — power and ground — accessed as SS.power and SS.ground, and created with the create_supply_set command; it lets UPF commands refer to 'the power and ground for this purpose' without hard-wiring specific net names everywhere.
  15. 15 What is the "primary power net" of a power domain?Beginner · The primary power net (together with the primary ground net) is the main supply that every cell inside a power domain is implicitly connected to, unless a cell has a special explicit connection otherwise — it's designated with set_domain_supply_net, and every power domain must have exactly one primary power net and one primary ground net.
  16. 16 What is the difference between primary power and backup/retention power?Beginner · Primary power is the main supply that gets switched off when a domain shuts down; backup (retention) power is a separate always-on supply that keeps specific logic — like a retention register's save-latch, or isolation/level-shifter control logic — alive even while the domain's primary supply is off, so state or valid outputs can be preserved.
  17. 17 What is the difference between a switched power supply and an alwayson power supply?Beginner · A switched power supply (sometimes called a virtual or internal supply) is one that a power switch cell can turn fully on or off — it disappears electrically when the domain shuts down — while an always-on power supply is the true, unswitched rail that stays live at all times, typically feeding the power switch itself and any always-on cells inside the shutdown domain.
  18. 18 What does "power-up" and "power-down" mean for a domain?Beginner · Power-down means turning off a domain's primary supply (via a power switch controlled by a sleep signal), while power-up means re-enabling that supply and bringing the domain back to normal operation — often through a controlled, staged sequence rather than an instantaneous switch, to manage in-rush ('rush') current and, if retention is used, to restore saved state.
  19. 19 What is a power state table?Beginner · A power state table (PST) is a structured list of the legal voltage/state combinations a design's supplies can be in — created in UPF with create_pst and populated with add_pst_state — used to formally define which supply-value combinations across all domains are valid operating modes.
  20. 20 What is a "valid" vs an "invalid" signal, and why does this matter when a domain shuts down?Beginner · A valid signal is one driven to a proper logic-0 or logic-1 level; an invalid signal is one that is floating or sitting at some intermediate voltage — which is exactly what happens to the output of a logic block when its power domain is shut down and its driver can no longer actively drive a clean logic level.
  21. 21 What is an isolation cell and why is it needed?Beginner · An isolation cell is a special standard cell placed on a signal that leaves a power domain, whose job is to hold that signal at a known, valid logic value whenever the driving domain is powered down.
  22. 22 What is the difference between an AND-type and an ORtype isolation cell (clamp value)?Beginner · An AND-type isolation cell clamps its output to logic-0 when isolation is active (an AND gate forces a 0 through one input); an OR-type isolation cell clamps its output to logic-1 when isolation is active (an OR gate forces a 1 through one input).
  23. 23 What is a level shifter and why is it needed?Beginner · A level shifter is a special cell placed on a signal crossing between two power domains that operate at different voltages, converting the signal's voltage swing from the source domain's level to the destination domain's level.
  24. 24 What is the difference between a low-to-high and a high-to-low voltage crossing?Beginner · A low-to-high (LH) crossing occurs when a signal travels from a lower-voltage domain into a higher-voltage domain; a high-to-low (HL) crossing occurs when a signal travels from a higher-voltage domain into a lower-voltage domain.
  25. 25 What is an enable level shifter (ELS)?Beginner · An enable level shifter is a single cell that combines the functions of isolation and level shifting, so one cell both clamps the output to a safe value when the source domain is off and translates the voltage level when the source domain is on.
  26. 26 What is a power switch and what does it do?Beginner · A power switch is a special cell (or bank of cells) placed on a domain's power or ground connection that can electrically connect or disconnect that domain from its supply rail, based on a control signal.
  27. 27 What is the difference between a header switch and a footer switch?Beginner · A header switch is placed on the VDD (power) side of a domain, between the always-on power rail and the domain's switched/virtual power rail; a footer switch is placed on the VSS (ground) side, between the domain's switched ground rail and the always-on ground rail.
  28. 28 What is a mother-daughter power switch configuration, and why would you stage the switch turn-on?Beginner · A mother-daughter switch configuration uses two power switch cells of different strength in series stages — a weaker 'daughter' switch that turns on first, followed by a stronger 'mother' switch — to bring a domain's supply up gradually instead of all at once.
  29. 29 What is a "virtual rail," and how is it different from the primary supply?Beginner · A virtual rail is the switchable (switched) power or ground net delivered to a shutdown domain through a power switch, as opposed to the always-on primary supply net that feeds the switch itself.
  30. 30 What is a switched ground net, and how does it relate to a footer switch?Beginner · A switched ground net is the ground rail delivered to a domain through a footer switch — it is electrically disconnected from the always-on ground (VSSG) whenever the footer switch is turned off.
  31. 31 What is an isolation control signal, and why must it stay "alive" even when a domain shuts down?Beginner · The isolation control signal is the logic net that tells an isolation cell whether to pass its data input through normally or clamp its output to the fixed isolation value; because isolation cells must clamp correctly at exactly the moment the source domain shuts off, this control signal must remain driven by an always-on source even though the domain it is protecting is powered down.
  32. 32 What is a retention signal (save/restore), and why is it needed?Beginner · SAVE and RESTORE (sometimes NRESTORE, active-low) are the control signals on a retention register that tell it to copy its current state into a backup latch before power is removed, and to copy that saved value back into the main flip-flop after power returns.
  33. 33 What does "save and restore" mean for a retention register?Beginner · "Save" is the operation of copying the current value of the main flip-flop into an internal backup latch just before the domain loses power; "restore" is the operation of copying that backup value back into the main flip-flop once power returns, so functional operation can resume from where it left off.
  34. 34 What is an always-on cell, and where is it physically placed?Beginner · An always-on cell is a standard cell that is functionally identical to an ordinary buffer, inverter, or similar gate, but is powered from a backup/true supply (VDDG/VSSG or VDDG/VSS) that never shuts off, and it is physically placed inside a shutdown domain to carry signals that must remain live through that domain's power-down period.
  35. 35 What is "power intent," and why do we need a separate language (UPF) to describe it?Beginner · Power intent is the complete specification of a design's power architecture — its power domains, supply nets, voltage levels, isolation/level-shifter/retention/switch strategies, and legal power states — captured separately from the RTL functional description; UPF (Unified Power Format) is the standardized, Tcl-based language used to write that specification.
  36. 36 What does the create_power_domain command do in UPF?Beginner · create_power_domain declares a new power domain — a named grouping of design elements (instances, ports) that share power management requirements — at a specified scope in the design hierarchy.
  37. 37 What is multivoltage design?Beginner · Multivoltage design is an architectural and implementation technique in which different blocks of a chip operate at different, fixed supply voltages, so that non-performance-critical logic can run at a lower voltage (saving power) while performance-critical logic runs at a higher voltage.
  38. 38 What is a voltage crossing between power domains?Beginner · A voltage crossing is any signal path where the driving side and the receiving side belong to power domains operating at different voltages, requiring a level shifter (and possibly isolation, if one side can also be shut off) to be inserted along that path.
  39. 39 What is a basic low-power verification check (e.g. check_mv_design), and what is it looking for?Beginner · check_mv_design is a command that checks the electrical correctness of a multivoltage design against its UPF power intent — verifying that supply voltages are properly assigned, that voltage-crossing and shutdown boundaries have the necessary isolation and levelshifter cells, and that no power-state or biasing rule violations exist.
  40. 40 Can you describe a basic low-power implementation mistake, like a missing isolation cell?Beginner · A missing isolation cell is a boundary between a shutdown domain and an always-on (or differently-timed) domain where no isolation strategy has clamped the crossing signal, so the receiver can see a floating or invalid voltage whenever the source domain is powered down.