What causes leakage power in a CMOS transistor?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
Leakage power in a CMOS transistor comes from current that flows even when the transistor is nominally 'off' — this comes from subthreshold conduction, gate-oxide tunneling current, and reverse-biased junction leakage.
Mentor Explanation
A beginner often assumes an 'off' transistor is a perfect open switch, but in reality there is always some residual current path. The important point is that these leakage mechanisms are strongly influenced by a transistor's threshold voltage, channel length, temperature, and process corner — which is exactly why leakage dependence on all of those factors is so well characterized in practice.
Example
This is why library vendors provide separate multi-Vt cell classes (HVt/SVt/LVt) — a highthreshold-voltage (HVt) cell is built specifically to suppress the subthreshold-conduction component of leakage at the cost of switching speed.
Why It Matters
Understanding leakage mechanisms explains why so many low-power techniques exist at the device/library level (multi-Vt selection, multi-channel-length libraries, back-biasing) rather than only at the RTL or architectural level — leakage is fundamentally a transistor-physics problem that implementation techniques try to manage.
Common Beginner Mistake
A common beginner mistake is thinking leakage only matters for very advanced/small nodes; in general, it is a first-class contributor to total power, with clear dependence on Vt, channel length, temperature, and process.
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