Physical Design Inputs, Pre-Floorplan Sanity, and Floorplanning: Interview Guide
Place & Route (PnR) physical implementation turns synthesized gate-level netlists into verified silicon layouts. Technical interviews evaluate structural input consistency, manufacturing grid alignments, pre-floorplan quality gates, macro floorplanning, power grid distribution, and blockage planning.
1. Core Physical Design Inputs & Library Formats
Before launching physical implementation in Synopsys IC Compiler II (ICC2) or Cadence Innovus, physical design engineers validate a comprehensive collateral checklist:
- Gate-Level Netlist (Verilog): Structural connectivity produced by RTL synthesis. Must be cleanly linked without floating inputs or unresolved black boxes.
- Timing & Power Libraries (.lib / .db): Non-Linear Delay Models (NLDM), Composite Current Source (CCS), or Effective Current Source Models (ECSM) providing cell delays, setup/hold constraints, leakage, and dynamic power.
- Physical Libraries (LEF / NDM): Contains cell abstract views, bounding boxes (PR boundary), pin geometries, and routing obstruction layers.
- Technology File / Tech-LEF: Defines metal layer stacks, dielectric constants, minimum width/spacing rules, preferred routing directions, and via definitions.
- Constraints & Power Intent: SDC timing constraints and IEEE 1801 UPF / CPF multivoltage architecture definitions.
2. Units, Manufacturing Grids & Pin Access
Modern FinFET physical design relies on precise coordinate grid systems:
2. Placement Site Grid: Standard cell row height and site width unit pitch
3. Routing Track Grid: Pitch and offset per metal layer for router wire centers
If standard cell pins fail to land precisely on legal routing track intersections, the detailed router generates local DRC spacing violations or requires expensive multi-cut jumper vias.
→ Practice Full Q&A: Manufacturing grids, routing tracks, and FinFET pin access3. Pre-Floorplan Sanity Quality Gates
Never proceed to floorplanning or placement without executing the Pre-Floorplan Sanity Gate. This quality review catches structural flaws that would otherwise waste weeks of runtime:
- Link Integrity: Verify zero unresolved black boxes or unlinked hierarchical modules.
- Constraint Validation: Check for unconstrained I/O ports, missing clock definitions, and unconstrained sequential pins using
check_timing. - High Fanout Nets: Identify resets, scan-enables, and global control nets that must be treated as ideal during early placement.
4. Die Sizing, Core Utilization & Aspect Ratio
The floorplan determines the physical boundaries, macro placement, power grid network, and I/O pad ring of the integrated circuit:
Aspect Ratio = Core Height / Core Width
A typical initial target utilization ranges between 65% to 75% to reserve whitespace for CTS buffer insertion, hold buffer ECOs, routing detours, and power dissipation decaps.
→ Practice Full Q&A: Floorplanning objectives, core utilization, and aspect ratio5. Macro Placement, Halos & Channel Blockages
Hard macros (SRAMs, ROMs, analog PHYs) must be positioned around the core periphery, keeping the center open for standard cell logic paths. Macro placement rules include:
- Keep macro pins facing toward the core standard cell area to minimize interconnect wire length.
- Maintain uniform macro orientation to ensure power strap and well connections align cleanly.
- Define Keepout Halos around macros to prevent standard cells from placing too close to macro pins, avoiding localized routing congestion and clock buffer blockage.
7. Place & Route Interview FAQs
What are the essential inputs required to start physical design implementation?
Logical netlist (Verilog), Liberty timing models (.lib/db), physical cell definitions (LEF/NDM/CEL), technology files (tf/tech-LEF), SDC timing constraints, UPF/CPF power intent, and RC interconnect extraction tables (ITF/TLU+).
Why must manufacturing grids, placement sites, and routing tracks align?
Misalignment causes DRC off-grid errors, pin access violations, and routing DRC shorts where standard cell pins or vias land off the manufacturing lithography grid.
What is the difference between a macro halo and a placement blockage?
A halo is attached directly to a specific macro and moves with it, preventing standard cell placement around its perimeter. A placement blockage is fixed to specific coordinates on the core canvas.