PnR Interview Questions and Answers

Physical design needs connectivity, cell models, process rules, timing requirements, and physical intent. These inputs jointly tell the tool what to build, what resources it can…

A gate-level netlist describes the circuit as instances of cells or modules connected by nets. It captures logical connectivity, rather than the final physical locations and wire…

RTL expresses intended register-transfer behavior; a mapped netlist expresses an implementation using particular cells. Place and route needs concrete cell models to place…

A Liberty library describes how cells behave electrically and logically under characterized conditions. It supplies information for timing, power analysis, and legal cell…

LEF describes reusable technology and cell physical abstractions; DEF describes the physical state of a particular design. One defines the building blocks and rules, while the…

NDM is ICC2's library/database framework. Reference libraries supply reusable blocks such as standard cells and macros; a design library stores the implementation blocks you are…

Technology data defines the physical vocabulary and implementation rules of the process: units, layers, vias, placement sites or tiles, and applicable routing information. It…

SDC expresses timing intent and the external electrical environment through constraint commands. It tells timing analysis which clocks and paths matter, and under what…

A number has engineering meaning only when its unit is known. Physical design combines distance, time, capacitance, resistance, voltage, current, and power, and the units can…

Database units, or DBU, represent physical coordinates as integers. A DEF declaration of 2000 database units per micrometer means that 2000 coordinate units represent a physical…

Width is the thickness of a wire measured across it. Spacing is the edge-to-edge gap between neighboring shapes. Pitch is the center-to-center distance between repeating…

It decides whether the imported, linked logical design and its timing intent are trustworthy enough to begin floorplanning; it does not judge placement or timing…

Verify the synthesised gate-level netlist, SDC, top name, handoff revision, logical libraries, reference/technology setup, modes, corners, scenarios, and available synthesis or…

A manifest connects every loaded file to a revision, producer, timestamp, mode, corner, and checksum so the run can be reproduced.

The current block, expected top name, hierarchy, and inventory must agree with the handoff record and synthesis summary.

Library identity and user units determine how cell behaviour and numeric constraint values are interpreted.

Import creates design objects from the Verilog; linking resolves every instantiated reference against the available design and library context.

Most ICC2 queries and reports operate on the current block, so correct syntax in the wrong context gives a polished but wrong answer.

An instance requests a module or library cell definition that the active reference context cannot supply.

A black box is acceptable only when the methodology deliberately abstracts its internals and still provides a controlled interface for timing and implementation.

It checks structural consistency such as connectivity defects that can survive parsing and linking.

An undriven object lacks a valid source; an unloaded output drives nothing. Either can be intentional at a boundary or evidence of lost connectivity.

A dangling pin or port is disconnected at an interface, while a no-load net has a driver but no meaningful sink; both require context.

Multiple active drivers can make a net functionally ambiguous unless an intentional bus or tri-state model explains them.

Constants can be correct mode straps or evidence that logic, a clock, or an enable was optimised away unexpectedly.

Compare ports, hierarchical cells, sequential cells, combinational cells, memories/macros, nets, and references with the synthesis handoff.

SDC object paths depend on the post-synthesis hierarchy and naming that ICC2 actually loaded.

Syntax validation proves commands can be parsed; it does not prove objects resolve, values model the interface, or constraints enter the correct mode/scenario.

A selector found no current design objects, commonly because hierarchy, names, buses, or optimisation changed.

Verify its source object, name, period, waveform, mode visibility, and reach to intended sequential clock pins.

A virtual clock has no physical design source and commonly represents an external launch or capture reference for I/O timing.

A generated clock derives its frequency, phase, or edges from a master/source relationship in the implemented logic.

They describe external timing relative to a clock; they are not delays of the block's input or output buffers.

These constraints model the electrical environment needed for meaningful cell delay and slew calculation at ports.

It diagnoses missing or inconsistent timing setup such as no-clock points, unconstrained endpoints, loops, generated-clock issues, and other selected categories.

Readiness requires matched provenance, resolved linking, classified structural findings, applied and reviewed SDC, complete clock/I/O intent, active scenario coverage, and owned…

A floorplan turns a logically valid design into a physical plan for boundaries, rows, macros, pins, channels, and reserved resources. It is the first proof that the design can…

The die is the outer design boundary; the core is the region used for standard-cell rows and most implementation objects. Core offsets are the distances from die sides to core…

Separate standard-cell area, hard-macro area, fixed or physical-only cell area, placeable area, reserved area, and whitespace. Mixing them makes utilisation meaningless.

Whitespace is the placeable area left after counted cells are assigned area. Target utilisation is the planned fraction of placeable area occupied by the explicitly counted…

Divide the counted placeable object area by the declared target utilisation. The result is a mathematical starting point, not a final implementable core.

Target utilisation is an input assumption; effective utilisation is the achieved counted occupancy after exclusions; local utilisation measures a smaller region. They answer…

Core aspect ratio is width divided by height. Equal-area rectangles can have different aspect ratios and very different routing and timing behaviour.

For area A and aspect ratio AR = width/height, width is sqrt(A x AR) and height is sqrt(A / AR). Keep units through every step.

Add the actual left and right offsets to core width, and the actual bottom and top offsets to core height. Do not double one offset unless both sides are truly equal.

A site defines legal placement increments, a row repeats sites for standard cells, and a routing track defines candidate wire centre lines. A row is not a track.

Row orientation must support the library’s legal cell orientations and power-rail alignment. Tiny row fragments consume bookkeeping space but may be unusable for real cells.

A hard macro has fixed dimensions and pin geometry, so its placement strongly shapes channels and rows. Standard cells are small, numerous, and placed later within legal rows.

Connectivity, dataflow, timing criticality, I/O affinity, bus sharing, clock/reset sources, power domains, pin sides, and macro dimensions should drive placement.

Orientation changes which side the pins face; alignment determines whether the macro sits on required grids. A geometrically legal rotation can still damage dataflow or power…

A channel is usable only when its width and geometry support signal tracks, facing pins, power straps, vias, shielding, buffers where needed, and technology spacing.

A keepout margin moves with its macro; a placement blockage is a fixed floorplan region. Both reserve space, but ownership and affected objects differ.

Core boundary cells protect and complete standard-cell row edges; inside/outside corner cells handle core or voltage-area corners; I/O-ring corner cells belong to the pad ring.…

Chip I/O pads or bumps connect the die to the package; top-level terminals represent design connections; macro pins belong to fixed macros; block pins expose hierarchical…

A feedthrough is a signal that enters a block and leaves it without being logically consumed there. It may shorten a top-level route, but it spends pin, routing, and possibly…

Early congestion estimates compare routing demand with available capacity in coarse regions. Overflow means demand exceeds capacity on one or more routing resources.

A legal pin obeys placement rules; an accessible pin also has a usable routing approach on an allowed layer and track without blockage or spacing conflict.

Rings, straps, rails, and vias consume area and routing capacity. Reserving their corridors early prevents a signal channel or pin plan from depending on tracks that power will…

A power domain describes logical power intent; a voltage area is the physical region where its cells may be placed. They are related but not interchangeable.

Distance, macro pin side, detours, hierarchy crossings, feedthroughs, congestion, buffering opportunity, and clock-source location change estimated interconnect delay.

A reviewable floorplan has deliberate boundaries, utilisation, usable rows, justified macro locations, feasible channels, constrained pins, early congestion/timing evidence, PG…

Input and output delays describe timing outside the block boundary relative to a reference clock. Maximum and minimum values expose the late and early interface behavior needed…

The handoff must identify real clock sources, generated-clock relationships, waveforms, and the timing assumptions for each operating mode. Clock-tree synthesis later implements…

RC technology models translate interconnect geometry into resistance and capacitance. TLUPlus is a layer-specific parasitic model used by ICC2 native extraction; layer mapping…

An RC technology file is a reusable extraction model for a process; SPEF records extracted parasitic networks for a particular design. One describes how to calculate parasitics,…

A mode describes how the design operates; a corner describes analysis conditions; an ICC2 scenario combines one mode and one corner. MMMC checks the design across multiple modes…

An initial floorplan defines the physical envelope and key constraints within which placement and routing will operate. It can be supplied as DEF or scripts, or generated during…

A hard macro needs compatible logical/timing and physical information, together with its interface and integration requirements. A black box in the netlist is not a complete…

UPF describes power intent: which logic belongs to power domains, how supplies and states are modeled, and what protection or state-preservation strategies are required. Logical…

Physical design needs the scan connectivity and allowed reordering constraints when it optimizes scan chains. A scan-inserted netlist describes connections; SCANDEF supplies…

Switching-activity files are conditional inputs. They improve activity-dependent power estimation and optimization, but are not universally required just to import and place a…

Validate relationships between files, not just each file independently. Names, units, revisions, physical technology, library models, and operating assumptions must describe the…

An unresolved reference means an instantiated design or cell cannot be bound to an appropriate definition. Debug the intended reference and library setup before altering the…

Audit timing coverage and the meaning of exceptions in every required scenario. A clean slack summary can hide paths that were never checked or were removed from analysis by an…

Load inputs in dependency order: establish the library and technology context, read and resolve the design, then apply compatible physical, power, and timing setup before…

A file's role depends on the stage. A routed DEF or extracted parasitic file can be an output of one run and an input to a later analysis or restart; the extension alone does not…

Successful import proves that the tool accepted data; clean timing proves only that the analyzed constraints passed. Neither proves that the files represent the intended chip or…

A strong input-readiness review asks whether the next implementation stage can start reproducibly with complete, consistent intent. It records evidence and ownership for…

Track pitch sets the distance between candidate routing centerlines. Track offset sets where the first centerline begins relative to the coordinate origin used by the track…

A placement site is a reusable unit of legal placement geometry. A row arranges sites across the floorplan, and a standard cell occupies a compatible number of sites while…

These grids constrain different things. The manufacturing grid quantizes allowed geometry coordinates; placement sites constrain legal cell placement; routing tracks suggest wire…

Fin pitch measures the center-to-center spacing between neighboring fins. Gate pitch measures the repeat spacing between neighboring gates. Contacted gate pitch, often called…

In a conventional FinFET device family, adding parallel fins increases effective channel width in discrete increments. The designer cannot choose an arbitrary continuous width in…

Report the actual FinFET grid and run its dedicated check before changing geometry. ICC2's grid contains x/y spacing and offsets that guide placement of cells containing FinFET…

Legality is the intersection of applicable rules, not a single snapped coordinate. A cell or macro can satisfy site placement while failing a FinFET boundary rule, or satisfy…

Establish identity and libraries, link, check structure/unbound objects, validate and apply SDC, inspect clocks/scenarios/exceptions, then run timing-health checks.

Use get_design_checks to confirm available check bundles and man to confirm syntax in the installed release.

It checks technology-file information, layer directions, and the presence of horizontal and vertical layers; it is only one readiness component.

Compare like-for-like scope and object classes, accounting for known handoff transformations rather than demanding unexplained equality.

Class totals reveal missing domains or views that a single overall cell count can hide.

Trace the object to interface intent, tie-off policy, black-box boundary, and synthesis log; intention requires recorded ownership.

The interface must have approved pin identity, timing boundary treatment, logical/physical views required for the next stage, revision, and owner.

Correlate reference-library order, cell view identity, PVT assignment, pin interface, and handoff version rather than trusting the instance reference text.

Compare ICC2 user units with Liberty declarations and the values expected by the STA handoff; inspect representative periods, slews, delays, and loads.

Functional intent commonly belongs to modes, operating-condition/parasitic intent to corners, combined analysis status to scenarios, and design-rule constraints can be…

A scenario can exist while setup, hold, or other required analysis is inactive.

Review errors, warnings, object-resolution messages, overridden constraints, current context, and resulting reports; parsing success is only the first gate.

Post-synthesis hierarchy and object names may differ from the intent source, causing selectors to resolve incorrectly or not at all.

Measure the collection and inspect representative names before applying a constraint; scope should be explainable and stable.

Compare reported period and edge waveform with the interface specification for each mode, including non-50-percent duty cycles when relevant.

The reported master, source object, target pin, divide/multiply factor, phase, and edge mapping must match real logic connectivity.

Use no_clock checks and targeted timing reports to correlate expected register groups with clock propagation through logical arcs.

It can be intentional mode multiplexing or a missing exclusivity/case relationship; the report requires mode-aware interpretation.

Every asynchronous, exclusive, or related declaration changes which crossings are analysed, so membership and mode scope must be reviewed.

There is no implemented clock tree, so built-tree skew and route latency do not exist; only justified early assumptions belong in the model.

Source latency models delay before the design clock source; estimated network latency is a methodology assumption inside the design and must not be confused with measured CTS…

Separate jitter, modelling margin, and setup/hold uncertainty according to methodology; ensure it is not duplicated by other margins.

An explicit pre-CTS transition can be a modelling assumption for cell delay; it is not a measured routed-clock slew.

For each timed input, confirm reference clock, edge, rise/fall scope, and both early and late interface intent where required.

A clock port defines timing reference behaviour and is not ordinary launched data; bulk get_ports * selectors can impose nonsensical data delay.

Verify receiving reference clock, edges, sign convention, min/max values, and whether the external requirement matches the interface specification.

A driving cell models a library-based source response, while explicit transition provides a direct slew assumption; methodology should choose and avoid conflicting intent.

Correlate load values with receiver and package assumptions, units, modes, and min/max analysis needs.

Inspect exact from/through/to membership, mode scope, precedence, affected path count, and functional reason.

Confirm the functional cycle relationship, start/end clocks, edge convention, and paired hold behaviour instead of applying a number mechanically.

Start from counted area, macro dominance, expected growth, physical-only cells, clock and hold buffering, spare strategy, routing access, PG reservation, voltage areas, and local…

Macro dimensions and channels often determine the outline before standard-cell area does. Dividing total area by one utilisation target can hide geometric infeasibility.

Recalculate required placeable area with the larger counted cell area, rebuild or resize the candidate, and compare rows, congestion, timing, and PG capacity using the same method.

Keep area, constraints, macro set, PG assumptions, and evaluation settings constant; compare path length, row continuity, channel capacity, pin affinity, congestion, and change…

Calculate ideal core dimensions, snap them to legal grids or row/site multiples, recompute actual area and utilisation, then add asymmetric offsets.

Compare row site names, library cell site compatibility, row height/width, orientation, voltage area, and the intended row pattern.

Measure its legal length, site alignment, voltage-area ownership, nearby keepouts, and whether intended cells plus required spacing can fit.

Compare row orientation and alternation with the standard-cell library’s legal orientations and power-rail convention.

Use flylines, bus width, path criticality, producer-consumer order, I/O affinity, clock/reset sources, and hierarchy to propose macro regions.

Edge placement can simplify external access and preserve central rows; internal placement can shorten central dataflow but creates more channel and blockage interactions.

They move pin walls relative to neighbours and may change supply-pin alignment. The macro outline can remain legal while routes become much longer.

Check macro origin, boundary, orientation, alignment point, and applicable block or FinFET grid. Movement, rotation, mirroring, and snapping are separate operations.

Start with usable routing layers and track pitches, subtract PG straps, blockages, via keepouts, shielding, and edge rules, then compare remaining directional capacity with…

They concentrate routes and pins, fragment rows, complicate PG continuity, and can create dead space that neither cells nor wires use well.

Choose by which objects must be excluded and for which stage: hard for broad placement exclusion, soft when later optimisation cells may be allowed, hard_macro to exclude hard…

A hard blockage excludes placement, a soft blockage can permit selected later optimisation use, a partial blockage limits occupancy, and a macro-only restriction targets hard…

Select library-approved left, right, top, bottom, inside-corner, and outside-corner cells for the actual row and voltage-area geometry, then report rules before insertion.

I/O guides reserve legal regions for I/O driver cells, while constraints describe package, protocol, power, and matching intent. place_io applies those rules to the intended…

Place block pins on legal sides, layers, tracks, and offsets according to top-level dataflow, routing corridors, bundles, and feedthrough intent.

Buses need deliberate ordering and corridor width; differential pairs need paired routing opportunity and consistent constraints. Both can be harmed by corner crowding or…

A feedthrough is better when the top-level distance and timing benefit exceeds the block’s pin, route, voltage-area, buffering, and ECO cost.

Classify original, created, buffered, reused, redundant, unused, pure, and mixed feedthroughs; then inspect the nets whose classification conflicts with intent.

Use the same floorplan version, coarse placement, scenarios, layer availability, PG/blockage assumptions, global-route mode, and report settings for every alternative.

Confirm data and constraints, locate demand and capacity, identify the physical cause, make the smallest causal change, then rerun the same measurement.

Pitch controls repetition, offset sets the first coordinate, direction selects X or Y track lines, and width can reserve a wire width. Technology rules decide legality.

Report its layer, side, and offset; compare with the track pattern, preferred direction, blockages, PG shapes, spacing rules, and neighbouring pins.

Overlay proposed ring, strap, rail, and via corridors on the same channel and congestion model used for signals, then compare remaining tracks and pin approaches.

Shape and size it for assigned cells, expected growth, legal rows, boundary cells, isolation/level-shifter/retention zones, switch corridors, macro compatibility, and supply…

Use the same netlist, SDC, scenarios, libraries, pre-CTS clock assumptions, coarse placement, and estimation method. Compare the same named paths and physical distances.

Include input and tool provenance, area assumptions, boundaries, rows/sites/tracks, macro and pin constraints, voltage areas, keepouts/blockages, reports, check results, images,…

Treat this as a hard stop and test competing causes: wrong current mode, empty clock source selector, broken generated/gated path, or mismatched hierarchy.

The name proves object creation only; inspect master, source, target, transformation, case analysis, disabled arcs, and real netlist connectivity.

False paths, case analysis, disabled arcs, inactive scenarios, or missing clocks can remove paths before they become unconstrained endpoints.

Assume the improvement is unproven until exact membership and functional justification show that only impossible paths were removed.

Correlate the constant with the active functional mode, source object, MUX behaviour, clocks, and disabled arcs.

It may be valid across modes, but within one scenario the MUX selection and exclusivity must reflect functional reality; ambiguity is a hard stop.

Distinguish an intentional feedback model from an accidental netlist loop and identify any automatic timing-arc break chosen by the tool.

An exception may be overridden, redundant, malformed, or dominated by another constraint; its presence in SDC does not mean it affects analysis.

The functional setup-cycle shift and corresponding hold relationship were not derived consistently from launch/capture edges.

Determine whether the disable comes from a library model, user constraint, case analysis, loop breaking, or mode-specific condition.

Compare scenario-mode associations, clocks, case analysis, I/O delays, and exception membership across modes.

If the missing scenario can change logical/timing readiness or design assumptions, it is a hard stop until the coverage matrix is restored.

Compare clocks, constants, I/O constraints, exceptions, active checks, and expected sequential populations separately; neither mode substitutes for the other.

Compare reported units and the same clock, delay, slew, and load values before comparing slack; keep each tool's logs separate.

Compare resolved library versions, PVT, operating conditions, cell identities, and scenario mapping before path arithmetic.

Compare clock creation, generated relationships, waveform, latency, uncertainty, case analysis, and mode scope without mixing command outputs.

It models the clock port as ordinary data and can create misleading boundary paths or constraints; selector scope is defective.

No; the sign can follow the receiving interface hold convention, but it must be derived and associated with the correct clock and edge.

The applied SDC must match the delivered netlist; mapping may need synthesis/STA regeneration, not local wildcard repair by PD.

Require named-object evidence, functional reason, affected modes, owner, risk, and a rerun-stable waiver; never waive only a message count.

Stop unless the approved abstraction and next-stage interface requirements are complete and the project explicitly accepts that model state.

Slack covers only analysed paths in active scenarios; missing clocks, exceptions, constants, inactive modes, or absent paths can make the result artificially clean.

No; each warning must be classified as a defect or justified intent with named objects, evidence, owner, risk, and review date.

Return defects in functional connectivity, synthesis structure, library release, interface timing intent, or mode definitions to their authoritative owner.

Proceed only when provenance matches, linking resolves, structure is classified, SDC semantics are reviewed, clocks/I/O/exceptions/scenarios provide intended coverage, and…

Treat legality and quality separately. Keep the legal baseline, identify the hot spot’s demand and capacity causes, change the smallest responsible physical choice, and rerun the…

Measure usable local area after rows, halos, blockages, voltage areas, and fixed objects, then compare with the cell and routing demand assigned there.

Use a scorecard with identical definitions and methods. Choose the shape whose combined row usability, macro legality, channels, pin access, PG reservation, congestion, timing,…

Do not force an illegal orientation. Test legal orientations, spacing, staggering, array order, pin-facing strategy, and surrounding routing layers; then change the array…

The original channel capacity estimate was incomplete. Recalculate usable signal tracks after PG widths, spacing, vias, and blockages, then negotiate macro spacing, strap…

Use asymmetric, evidence-based margins where supported: reserve space where pins, vias, routing, or optimisation cells need it, and avoid wasting quiet sides.

Check voltage-area geometry, row orientation, inside versus outside corners, library-specific rules, legal cell orientations, and whether the correct insertion flow ran.

Treat package pins as constraints, then adapt macro locations, block pins, feedthroughs, aspect ratio, and routing corridors around them. Escalate only when the package interface…

Compare top-level delay saved with block pin count, alignment, route capacity, buffering, voltage-area compatibility, reuse, and ECO flexibility. The system owner and block owner…

Treat this as a pin-access defect. Report the pin geometry and nearby tracks/resources, then move, spread, reorder, or re-layer it within the interface constraints.

It proves the earlier signal-only model was incomplete, not that power planning should be ignored. Rebalance shared routing resources and floorplan geometry.

Compare assigned cell area and growth with legal rows, guard bands, enclosure, boundary cells, switch/interface-cell zones, macro overlap, and supply access.

Identify which named paths improved and which local resources failed, then test a change that preserves the timing benefit while relieving concentrated demand.

Compare floorplan write-out, checkpoint, tool version, app options, scenarios, libraries, constraints, placement seed, PG/blockage assumptions, and report settings before…

Check control type, shape, side lengths or ratios, boundary points, orientation, offsets, retained objects, site definition, and whether an old boundary was intentionally kept.

No. It can break manufacturing/block-grid requirements, pin access, array alignment, or power connectivity; treat it as a hard stop for that macro placement.

Confirm technology-layer definitions, preferred directions, pitch, offset, width, core coverage, restrictions, and whether tracks were intentionally regenerated. Do not create…

Check stale constraints, fixed status, orientation-dependent dimensions, snap movement, relative-location constraints, voltage areas, and which floorplan version was loaded.

They inflate nominal placeable area and can mislead early placement, utilisation, or legality. Determine whether the rows should be cut, made transparent by methodology, or…

Identify whether package/interface intent, block pin constraints, routing blockage, or PG reservation is authoritative, then negotiate a geometry that preserves the required…

Separate classifications, inspect named nets and blocks, and compare each with intended topology, pin pairs, buffering, and reuse policy. The categories require different…

Stop or iterate if required PG sources, rings/straps/rails, macro pin access, switch corridors, or via paths cannot fit without destroying signal capacity. Planning must reserve…

Inspect actual macro pin sides, route corridor, blockages, voltage areas, feedthrough options, hierarchy crossings, congestion, and buffering sites. Centre distance can hide a…

Use one scorecard with declared definitions and identical methods for area/utilisation, usable rows, macro legality, channels, pins, congestion, PG reservation, voltage areas,…

Proceed only when boundaries, rows, macros, channels, pins, feedthroughs, tracks, PG reservation, voltage areas, congestion, and early timing are physically credible and…