upstream launch FF OUR DESIGN port_in port_out downstream capture FF set_input_delay set_output_delay What does set_output_delay do?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
set_output_delay models how much time before the external clock edge the data must leave an output port, capturing the timing budget consumed by whatever sits outside the chip after the output pin.
Example
The command set_output_delay 250 -clock clk [get_ports port_out] tells the tool that data at port_out must be ready 250 ps before the external clk edge that will capture it downstream.
Why It Matters
This constraint lets the tool properly analyze reg2out paths, ensuring the chip's internal logic finishes early enough to satisfy whatever external device or board-level requirement is waiting on that output.
Command
set_output_delay 250 -clock clk [get_ports port_out] -- reserves 250 ps of
external budget before the clk edge that captures port_out downstreamMentor Note — Common Mistake
Forgetting to specify an output delay at all, which causes the tool to assume the output has the entire clock period to settle — masking a real setup problem that would only show up once connected to the external system.
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