Level 1 · Foundations

Beginner STA Interview Questions

Build the vocabulary and timing-path mental model needed to read constraints and reports accurately.

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What to practise at this level

Build the vocabulary and timing-path mental model needed to read constraints and reports accurately.

  1. 01 What is Static Timing Analysis (STA), and why do we need it?Beginner · STA is a method for checking that a synchronous digital chip meets its timing requirements without actually simulating it with input vectors.
  2. 02 Why can't circuit simulation alone verify that a chip meets timing?Beginner · Simulation only checks the specific input patterns (vectors) you feed it, while STA statically examines every timing path in the design regardless of what vectors you would have run.
  3. 03 What is a timing path?Beginner · A timing path is the route a signal takes from a startpoint, through combinational logic, to an endpoint.
  4. 04 What are startpoints and endpoints of a timing path?Beginner · Startpoints are where a path begins — input ports and clock pins of sequential elements; endpoints are where it ends — output ports and the data-input pins of sequential elements.
  5. 05 What are the four categories of timing paths (reg2reg, in2reg, reg2out, in2out)?Beginner · These four categories describe where a path begins and ends: reg2reg (flip-flop to flipflop), in2reg (input port to flip-flop), reg2out (flip-flop to output port), and in2out (input port straight through to output port).
  6. 06 How do you define a clock in SDC, and what does the create_clock command do?Beginner · You define a clock using SDC (Synopsys Design Constraints), the industry-standard Tclbased format for describing a design's timing intent, and the create_clock command is what actually establishes a clock's period and waveform on a given port.
  7. 07 What is data arrival time?Beginner · Data arrival time is when a signal actually reaches a given node, computed by adding up all the delays along the path leading to it.
  8. 08 What is data required time?Beginner · Data required time is the latest moment (for a setup check) or earliest moment (for a hold check) that a signal is allowed to arrive at its destination.
  9. 09 What is a setup check, and what is setup time?Beginner · A setup check verifies that data launched by one clock edge arrives at the capturing flipflop's D pin early enough — specifically, at least a setup time (Tsu) before the capturing edge; it is a max-delay check.
  10. 10 What is a hold check, and what is hold time?Beginner · A hold check verifies that data launched by a clock edge does not arrive at the capturing flop too soon after that same edge — the data must stay stable until a hold time (Th) after the edge; it is a min-delay check that does not depend on the clock period at all.
  11. 11 What is slack?Beginner · Slack is the margin by which a timing check passes or fails — the difference between the required time and the arrival time.
  12. 12 What do positive slack and negative slack mean?Beginner · Positive slack means a path has margin to spare and passes its timing check; negative slack means the path violates its check and fails.
  13. 13 What are launch and capture flip-flops?Beginner · The launch flip-flop is the one that sends data out on a clock edge (the launch edge), and the capture flip-flop is the one that captures that data on a later clock edge (the capture edge).
  14. 14 What does set_input_delay do?Beginner · set_input_delay models how long after a clock edge the data actually arrives at an input port, telling the STA tool how much of the clock period is already used up before the signal even enters the chip.
  15. 15 upstream launch FF OUR DESIGN port_in port_out downstream capture FF set_input_delay set_output_delay What does set_output_delay do?Beginner · set_output_delay models how much time before the external clock edge the data must leave an output port, capturing the timing budget consumed by whatever sits outside the chip after the output pin.
  16. 16 What is clock uncertainty?Beginner · Clock uncertainty is a margin subtracted from the available timing budget to account for imperfections in the clock, chiefly jitter, plus any additional margin or guardband the designer wants to add.
  17. 17 What is clock latency, and what's the difference between source latency and network latency?Beginner · Clock latency, also called insertion delay, is the absolute time it takes the clock to travel from its source to a flip-flop's clock pin; it splits into source latency, the delay from the clock's true origin to its definition point, and network latency, the estimated delay through the on-chip clock tree itself.
  18. 18 What is clock skew?Beginner · Clock skew is the difference in clock arrival time between two points — specifically, capture arrival time minus launch arrival time.
  19. 19 What is combinational (logic) delay in a timing path?Beginner · Combinational (logic) delay is the portion of a timing path's delay that comes from the chain of logic gates and interconnect between the launch point and the capture point, as opposed to the flip-flop's own internal delay.
  20. 20 What is cell delay?Beginner · Cell (gate) delay is the time from when an input of a logic cell crosses its switching threshold to when the output crosses its threshold — essentially the internal switching delay of that gate.
  21. 21 What is net delay (interconnect delay)?Beginner · Net delay is the time a signal takes to travel along a wire from one cell's output pin to the next cell's input pin, after the driving cell has already produced its output.
  22. 22 How do you read a basic timing report from report_timing?Beginner · A report_timing output walks the path hop by hop from the startpoint flop to the endpoint flop, showing an incremental delay (Incr) and a running total (Path) at each point, then compares the data arrival time to the data required time to get slack.
  23. 23 What is an SDC file, and what are 'basic timing constraints'?Beginner · SDC stands for Synopsys Design Constraints, and it is the industry-standard Tcl-based text format used to write down a design's timing intent for the STA tool to read.
  24. 24 What is a setup violation, and what does it mean physically?Beginner · A setup check makes sure data arrives at a flop's input early enough, before the capturing clock edge, with some margin to spare. A setup violation means slack is negative, so the data arrived too late.
  25. 25 What is a hold violation, and what does it mean physically?Beginner · Slack, in general, is required minus arrival, and a violation of any kind (setup or hold) simply means that slack has gone negative for that check.
  26. 26 What is slew (transition time), and why does it matter?Beginner · Slew, also called transition time, is the amount of time it takes a signal's waveform to swing between two defined threshold points, commonly the 20 percent and 80 percent levels.
  27. 27 What is a standard cell timing library (Liberty), and what does it contain?Beginner · A standard-cell library holds the characterized timing (and power) data for every logic cell used in the design, and Liberty (.lib) is the structured, text-based format used to write that characterized data down.
  28. 28 What is NLDM (Non-Linear Delay Model)?Beginner · NLDM stands for Non-Linear Delay Model. It represents a cell's timing arc delay (and output transition) as a two-dimensional lookup table, indexed by the input slew coming into the cell and the output capacitive load the cell is driving.
  29. 29 What are PVT corners, and why does timing change across them?Beginner · PVT corners refer to combinations of Process, Voltage, and Temperature conditions at which a standard cell's timing is characterized. A library is not one single file, it ships as a set of files, one per PVT condition.
  30. 30 What is the difference between an ideal clock and a propagated clock?Beginner · An ideal clock is modeled as reaching every flop instantly, or with just a fixed, uniform latency number, before any real clock tree/network has even been built. A propagated clock is timed through the actual, built clock network, capturing real insertion delay and real skew between different flops.
  31. 31 What is WNS (Worst Negative Slack)?Beginner · WNS, or Worst Negative Slack, is simply the single most negative slack value found anywhere in the design among all the violating (failing) paths.
  32. 32 What is TNS (Total Negative Slack)?Beginner · TNS, or Total Negative Slack, is the sum of all the negative slack values across every violating path in the design, not just the worst one.
  33. 33 What is a generated clock?Beginner · A generated clock is a clock signal that is derived from a master clock (or from another already-generated clock) by some on-chip logic, such as a divider, a clock gate, a multiplexer, or an inverter, rather than coming directly from an external clock source.
  34. 34 What is a false path?Beginner · A false path is a path through the netlist that STA is able to trace topologically (structurally, following the logic connections) but that can never actually be exercised during real functional operation of the chip.
  35. 35 What is a multicycle path?Beginner · A multicycle path is a path where the design's intended behavior allows the data more than a single clock cycle to travel from its launching flop to its capturing flop, rather than the default assumption of exactly one cycle.
  36. 36 What does the check_timing command do, and why should you run it before trusting any report?Beginner · check_timing is a constraint sanity check: it scans the design and SDC setup for problems like endpoints that were never constrained, flops that have no clock reaching them, generated clocks whose source can't be found, and combinational loops.
  37. 37 What are parasitics, and what is SPEF?Beginner · Parasitics are unintended electrical properties, resistance and capacitance, that physically exist in interconnect (metal wires and vias) simply because those wires are made of real conductive and dielectric materials, not because any designer deliberately added them. SPEF (Standard Parasitic Exchange Format) is the industry-standard text format used to represent those extracted values for every net in a design.
  38. 38 What is the difference between pre-layout and post-layout STA?Beginner · Pre-layout STA runs before physical placement and routing exist, so it relies on estimated or wire-load-based parasitics as a stand-in for real wires. Post-layout (postroute) STA runs after the chip has actually been placed and routed, using parasitics extracted from the real routed geometry (via SPEF), which is much closer to how the silicon will actually behave.
  39. 39 What are the major input files STA needs to run (netlist, library, SDC, parasitics)?Beginner · A standard timing run is fed by several key inputs together: the netlist (the actual gatelevel logic connections), the timing library (characterized cell delay/timing data, in Liberty format), the SDC file (the design's timing intent and constraints), and parasitic data such as SPEF (extracted or estimated wire resistance/capacitance), along with MMMC configuration for multiple corners/modes.
  40. 40 What is timing signoff?Beginner · Timing signoff is the formal declaration that a design meets all of its timing requirements under the agreed-upon conditions, and is therefore considered safe to tape out (send off for manufacturing).