BeginnerQuestion 21 of 40Source PDF page 21

What is net delay (interconnect delay)?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

Net delay is the time a signal takes to travel along a wire from one cell's output pin to the next cell's input pin, after the driving cell has already produced its output.

Example

In the report_timing example, the hop from u3/Z to reg_b/D is described as a 'net' step contributing 0.07 to the running path total, on top of all the cell delays that came before it.

Why It Matters

Wires are made of real conductive material, so they carry actual resistance and capacitance. Those parasitics slow the signal down, and as chips shrink, wire delay becomes a bigger share of the total path delay alongside cell delay.

Mentor Note — Common Mistake

Don't assume wires are 'free' or instant just because they look thin on the layout. Ignoring net delay is exactly the kind of blind spot pre-layout, wireload-based estimates create.

Visual explanationSTA context: What is net delay (interconnect delay)?
STA context: What is net delay (interconnect delay)?A three-step concept map summarizes the focus, core answer, and practical verification for What is net delay (interconnect delay)?Question focusWhat is net delay(interconnect delay)?Core answerNet delay is the time asignal takes to travelalong a…Verify in practiceConfirm the path,constraints, clockassumptions, and timingreport.Understand → explain the mechanism → verify the assumptions

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