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What does set_input_delay do?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

set_input_delay models how long after a clock edge the data actually arrives at an input port, telling the STA tool how much of the clock period is already used up before the signal even enters the chip.

Example

The command set_input_delay 300 -clock clk [get_ports port_in] tells the tool that data at port_in arrives 300 ps after the clk edge, before it starts through the chip's internal logic.

Why It Matters

Without this constraint, the tool would assume input data arrives at the clock edge with zero delay, which is unrealistic and would let in2reg paths pass timing checks that would actually fail once you account for external delay.

Command

set_input_delay 300 -clock clk [get_ports port_in] -- models 300 ps of external delay before data reaches port_in relative to the clk edge

Mentor Note — Common Mistake

Leaving out the -clock switch — since a reference clock is almost always required, an input delay without it either errors out or attaches to the wrong clock, producing incorrect required times.

Visual explanationSTA context: What does set_input_delay do?
STA context: What does set_input_delay do?A three-step concept map summarizes the focus, core answer, and practical verification for What does set_input_delay do?Question focusWhat doesset_input_delay do?Core answerset_input_delay modelshow long after a clockedge the data actuallyarrives…Verify in practiceset_input_delay 300-clock clk [get_portsport_in] -- models 300ps of external…Understand → explain the mechanism → verify the assumptions

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