What this chapter covers

A timing analysis is only as trustworthy as the environment it assumes. This chapter is how you tell the tool the truth: clocks (period, waveform, latency, uncertainty), boundary context (input/output delay, driving cell, external load), exceptions (false paths, multicycle paths, min/max delay), plus the libraries, netlist, and parasitics that must be read together. Most real STA bugs are constraint bugs.

Every block and top-level run starts here. Constraint development, review, and equivalence across synthesis → P&R → signoff is daily timing-engineering work. A missing clock or unconstrained port is a silent hole, not a tool crash.

Worked example

A complete environment reads the netlist, links timing libraries, annotates SPEF, defines create_clock on the source, applies set_input_delay/set_output_delay versus that clock, then runs check_timing before trusting WNS. If an input port has no input delay, that in-to-reg path is not a “clean” path — it was never checked.

A common misconception

Running report_timing before check_timing, or copying a block SDC to the top without re-validating clocks and exceptions. Over-broad set_false_path “to clean the report” is the classic silent escape.

Sample interview answers

What belongs in a trustworthy STA environment? Matched libraries and netlist, clocks, I/O delays, parasitics, operating conditions/analysis views, and exceptions that are justified — then check_timing.

Why is an unconstrained port dangerous? STA does not invent external timing. An unconstrained input or output is silently omitted from the checks you think you ran.

How do you confirm clocks actually reached sequential cells? Propagate clocks and inspect unconstrained registers / no-clock reports from check_timing, not only a green WNS number.

The paid chapter walks environment bring-up, check_timing categories, SDC object queries, and interview questions tied to PrimeTime constraint reports.

SDC library: SDC handbook · Next: Timing verification · Related: check_timing, create_clock

💡 Key Technical Topics Covered

  • PrimeTime Tcl Environment Setup
  • Operating Conditions & PVT Selection
  • Set Case Analysis & Logic Constant Constraints
  • Wire Load Model Selection

🎯 VLSI Physical Design Interview Questions Addressed

  • How do you configure PrimeTime for multi-corner analysis?
  • What is set_case_analysis used for in STA?
  • How do you check for unconstrained paths in PrimeTime?