What this chapter covers

This is where STA does its defining job: compute arrival, required time, and slack for setup (max) and hold (min) at sequential endpoints, plus recovery/removal, pulse-width, and clock-gating checks. It is also how you read report_timing: every line of the arrival/required stack, path groups, and why a path failed so it can be fixed.

Every timing iteration and every signoff corner/mode run produces these reports. Fluency here is the difference between running STA and closing timing.

Worked example

A setup path dump shows launch clock arrival, clock-to-Q, combinational data delay, capture clock arrival, library setup, and uncertainty. Slack = required − arrival. If the path fails, the largest data-path increment is the usual sizing/buffering target; if the clock path dominates, the fix is CTS or uncertainty — not another AND gate.

A common misconception

Fixing setup with min-delay techniques (or hold with max-delay techniques), or declaring “timing is clean” from a single-corner WNS without path coverage, exceptions review, and the specialized checks. A zero-WNS report can still hide unconstrained endpoints.

Sample interview answers

What does a setup check actually compare? Whether data launched by one edge is stable soon enough before the capturing edge, after clock path, data path, library setup, and uncertainty.

Why can hold fail when setup is easy? Hold has no period in the equation. Short data paths plus late capture clocks fail even at low frequency.

Is WNS = 0 enough for signoff? No. You still need coverage (constrained endpoints), justified exceptions, the specialized checks, and the full mode×corner matrix.

The paid PDF annotates full PrimeTime path reports, setup-versus-hold ECO order, recovery/removal and pulse-width examples, and the chapter interview bank.

Previous: STA environment · Next: Interface analysis · Related: Slack, ECO timing flow, Expert STA

💡 Key Technical Topics Covered

  • PrimeTime report_timing Debug Flow
  • Setup Violation Fixing (Buffering, Sizing, Swap)
  • Hold Violation Fixing (Delay Cell Insertion)
  • Bottleneck & Critical Path Analysis

🎯 VLSI Physical Design Interview Questions Addressed

  • How do you analyze a PrimeTime timing report line by line?
  • What are the steps to fix a setup violation without causing hold failure?
  • Why do we fix hold timing only after setup timing is clean?