BeginnerQuestion 6 of 40Source PDF page 9

How do you define a clock in SDC, and what does the create_clock command do?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

You define a clock using SDC (Synopsys Design Constraints), the industry-standard Tclbased format for describing a design's timing intent, and the create_clock command is what actually establishes a clock's period and waveform on a given port.

Example

The command create_clock -name CLK -period 2.0 [get_ports clk] defines a 500 MHz clock by setting its period to 2.0 ns on the port named clk.

Why It Matters

Every setup and hold check in the whole design is ultimately measured against the clock definitions you create, so an incorrect or missing create_clock command corrupts every timing calculation downstream of it.

Command

create_clock -name CLK -period 2.0 [get_ports clk] -- defines a 500 MHz clock (period in ns) on port clk

Mentor Note — Common Mistake

Garbage in any one of these inputs — especially SDC — gives garbage timing results, so a typo in the clock period (like writing 20.0 instead of 2.0) silently changes every timing budget in the design.

Visual explanationClock waveform created by create_clock
Clock waveform created by create_clockA ten nanosecond clock period with a fifty percent duty cycle has rising edges at zero, ten, and twenty nanoseconds.Period = 10 ns0 ns10 ns15 ns10

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