Chapter 05: Delay Calculation

What this chapter covers

This chapter is the connective tissue between Liberty cell models and extracted RC: how the delay calculator turns input slew, output load, timing arcs, and parasitics into cell delay, net delay, and a propagated output slew for the next stage. It covers NLDM table interpolation, effective capacitance, CCS/ECSM current-source models, and why a path’s arrival time is the sum of those stage results — not a single “gate delay” number.

You use it every time you read report_timing, run update_timing, or debug why PrimeTime’s delay disagrees with another tool or with silicon. It is also why sizing, buffering, and load changes move slack: they change the interpolation point in the tables.

Worked example

A buffer’s cell delay is interpolated from the library at the actual input slew and the downstream load (pin C plus annotated net C). That cell’s output slew becomes the next cell’s input slew. If the net is long, net delay from the SPEF RC can exceed the cell delay. Slack on the path is the accumulation of those stage delays against the capture clock’s required time.

A common misconception

Reading only the cell delay column and ignoring slew degradation, or assuming NLDM remains accurate on a highly resistive net where a current-source model (CCS) is required. Another trap is correlating two tools that used different load models or different SPEF reduction.

Sample interview answers

What inputs does cell-delay calculation need? The timing arc, the input transition at the driver pin, and the output load seen by that pin — from pin capacitance plus annotated parasitics.

Why does output slew get propagated? Each stage’s output transition is the next stage’s input transition. Ignoring slew underestimates later cell delays on a slow chain.

Where does net delay come from? From the annotated RC (SPEF) or, before extraction, from a wire-load model. Signoff should not still be on wire-load for routed nets.

The paid chapter walks NLDM interpolation numerically, contrasts Ceff versus full RC, shows delay-calculation debug reports, and includes the interview set with figures from the STA handbook.

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