What this chapter covers

At nanometer nodes, wires are first-class delay. This chapter covers the physical origin of interconnect resistance and capacitance, lumped versus distributed RC, Elmore delay, extraction from layout (technology files, ITF, TLU+), SPEF as the handoff format, RC corners (Cmax/Cmin, RCmax/RCmin), and coupling capacitance that later becomes crosstalk.

Engineers use this whenever a StarRC (or equivalent) run produces SPEF for PrimeTime or Fusion Compiler, when they choose RC corners in an MMMC matrix, and when placement or routing trades wire delay against congestion. Without annotated parasitics, STA is guessing net delay.

Worked example

A driver-to-receiver net is extracted as a distributed RC tree, reduced, and written to SPEF. Signoff STA annotates that SPEF, then the delay calculator reports net delay plus slew at each receiver. Changing only the RC corner (for example Cmax versus Cmin) can move the same net from setup-critical to hold-critical because capacitance and resistance are worst-cased in opposite directions.

A common misconception

Treating pre-route estimated wire delay as signoff, or assuming one SPEF covers every RC corner. Extraction is a modeling pipeline with approximations; correlation gaps appear when the SPEF, reduction, and delay calculator do not match the node you are signing off.

Sample interview answers

What is SPEF used for in STA? SPEF carries extracted parasitic R and C for nets so the delay calculator can replace wire-load estimates with geometry-based net delay and slew.

Why do we analyze more than one RC corner? Cmax/Cmin and RCmax/RCmin bound fabrication and extraction variation. Setup often cares about the slow RC extreme; hold often cares about the fast one.

Does coupling capacitance belong in parasitics or only in SI? Coupling C is extracted with the parasitics. Quiet-aggressor coupling still loads the victim; switching aggressors become the crosstalk chapter’s delay and noise analysis.

The paid PDF adds extraction-flow diagrams, SPEF/RC-corner worked examples, Elmore versus distributed delay comparisons, and the chapter’s 80 interview questions with diagrams — material that stays in the handbook rather than on this landing page.

Library: STA handbook · Next: Delay calculation · Related: What is SPEF?, RC corners, MMMC guide

💡 Key Technical Topics Covered

  • Standard Parasitic Exchange Format (SPEF) Syntax
  • Elmore Delay & DSPF/RSPF Parasitics
  • Resistance-Capacitance (RC) Net Reduction
  • Wire Load Models vs Actual Extraction

🎯 VLSI Physical Design Interview Questions Addressed

  • How does Elmore delay calculate interconnect delay?
  • What is the difference between SPEF and DEF files?
  • How does net resistance affect signal transition time?