STA Library • Chapter 04

Chapter 04: Interconnect Parasitics

Parasitic extraction (SPEF, DEF), Elmore delay model, RC interconnect trees, and wireload models in physical design.

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Authored by VLSI Veteran (9+ Years Experience)

Practical physical design signoff insights, real Primetime flows, and interview preparation.

💡 Key Technical Topics Covered

Standard Parasitic Exchange Format (SPEF) Syntax
Elmore Delay & DSPF/RSPF Parasitics
Resistance-Capacitance (RC) Net Reduction
Wire Load Models vs Actual Extraction

🎯 VLSI Physical Design Interview Questions Addressed

How does Elmore delay calculate interconnect delay?
What is the difference between SPEF and DEF files?
How does net resistance affect signal transition time?

← Chapter 03: Standard Cell Library Chapter 05: Delay Calculation →