What this chapter covers

Static Timing Analysis (STA) is a vectorless method for proving that a synchronous chip meets setup and hold requirements at every analyzed path. Instead of simulating selected stimulus, an STA tool walks the structural timing graph, computes arrivals and required times, and reports slack so signoff can proceed with evidence rather than hope.

Engineers use STA because gate-level simulation cannot exhaustively cover every launch-to-capture combination, clock-domain relationship, and operating condition that a modern ASIC must survive. This chapter introduces that signoff mindset: what STA checks, why simulation alone is insufficient, and how setup and hold equations sit inside a physical-design flow that later includes constraints, libraries, parasitics, and PrimeTime reports. You will also see where STA sits relative to synthesis, place-and-route, and tapeout, so later chapters on libraries and parasitics have a place to land.

Key takeaways

  • STA is exhaustive over the paths and checks it is told to analyze; it does not prove functional correctness.
  • Setup asks whether data is stable soon enough before the capturing edge; hold asks whether it remains stable long enough after that edge.
  • Clock path, data path, and skew all belong in the same equation — treating “logic delay” as the whole story is a common beginner mistake.
  • Signoff STA is a flow, not a single command: libraries, SDC, parasitics, and analysis views must be trustworthy before a green WNS number means anything.

Interview angle: if asked why we still need STA when we already simulate, say that simulation is stimulus-limited while STA is structural; then name setup versus hold and one thing STA does not check (logic bugs, or unconstrained paths).

Open the PDF reader for diagrams, timing-path sketches, and PrimeTime report examples that accompany this chapter.

STA handbook · Next: STA Concepts · Related questions: What is STA?, Why simulation is not enough, What is a timing path?

Sample interview answers

Why is STA vectorless compared with dynamic simulation? STA walks the structural timing graph and checks every analyzed launch-to-capture combination without stimulus vectors. Simulation only proves the patterns you ran.

What is a setup violation, and how do you fix it? Setup fails when data arrival is later than the required time before the capturing edge. Fixes attack the late data path, launch/capture clock relationship, or the constraint that made the check too tight — not “add a buffer” as a reflex.

Explain clock skew, jitter, and uncertainty. Skew is capture-minus-launch clock arrival. Jitter is period/edge variation at the source. Uncertainty is the SDC guardband that tightens setup and hold to cover residual clock error you are not modeling elsewhere.

Related questions: What is STA?, Why simulation is not enough, What is clock skew?

💡 Key Technical Topics Covered

  • STA vs Dynamic Gate-Level Simulation
  • Setup and Hold Time Fundamentals
  • Data Path, Clock Path & Clock Skew
  • ASIC Physical Design Signoff Flow

🎯 VLSI Physical Design Interview Questions Addressed

  • Why is Static Timing Analysis vectorless compared to dynamic simulation?
  • What is setup time violation and how do you fix it?
  • Explain clock skew, jitter, and uncertainty in physical design.