BeginnerQuestion 2 of 40Source PDF page 7

Why can't circuit simulation alone verify that a chip meets timing?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

Simulation only checks the specific input patterns (vectors) you feed it, while STA statically examines every timing path in the design regardless of what vectors you would have run.

Example

If a chip has millions of paths, simulating enough vectors to stress every single path directly would be impractical, but STA computes the delay along each path in one static pass over the whole netlist.

Why It Matters

Because timing failures can hide in paths that your simulation vectors never happen to activate, relying on simulation alone risks silicon that fails in the field even though it 'passed' every test you thought to run.

Mentor Note — Common Mistake

Assuming that a design which simulates correctly at some clock frequency must therefore meet timing everywhere — simulation coverage is never truly exhaustive the way static path-by-path analysis is.

Visual explanationSTA context: Why can't circuit simulation alone verify that a chip meets timing?
STA context: Why can't circuit simulation alone verify that a chip meets timing?A three-step concept map summarizes the focus, core answer, and practical verification for Why can't circuit simulation alone verify that a chip meets timing?Question focusWhy can't circuitsimulation alone verifythat a chip meetstiming?Core answerSimulation only checksthe specific inputpatterns (vectors) youfeed it, while…Verify in practiceConfirm the path,constraints, clockassumptions, and timingreport.Understand → explain the mechanism → verify the assumptions

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