BeginnerQuestion 3 of 40Source PDF page 7

What is a timing path?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

Short Answer

A timing path is the route a signal takes from a startpoint, through combinational logic, to an endpoint.

Example

A simple path might begin at a flip-flop's clock pin, pass through a chain of AND and OR gates, and end at the data-input pin of the next flip-flop.

Why It Matters

Every delay number and every setup/hold check in STA is computed with respect to a specific timing path, so understanding what constitutes 'a path' is the foundation for reading any timing report.

Mentor Note — Common Mistake

Thinking a path is just a wire — it actually includes both the combinational logic cells and the interconnect between the startpoint and endpoint, and its delay is the sum of all of it.

Visual explanationAnatomy of a register-to-register timing path
Anatomy of a register-to-register timing pathA launch flip-flop drives combinational logic and interconnect before a capture flip-flop samples the data.Launch FFCLK → QLogic + NetData delayCapture FFD sampledTiming analysis compares data arrival against the capture requirement

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