Know Your Inputs · Episode 1 · 31 min
Know Your Inputs: The 6 Files Every Physical Design Flow Starts With
Netlist, SDC, Liberty, tech LEF, cell LEF and MMMC, explained line by line on a small demo design (tiny_core), so you can see what the PnR tool actually reads and why each line matters.
What this video covers
- Gate-level netlist (.v): instances, nets, and why every cell name must exist in the library
- SDC (.sdc): clock, input/output delay, driving cell and load
- Liberty (.lib): cell area, pin capacitance, delay tables, setup and hold
- Technology LEF: metal layers, direction, pitch, width, spacing, site
- Cell LEF: cell size, pin shapes, power rails, macro blockages
- MMMC: library sets, RC corners, delay corners, analysis views