What this chapter covers

A Liberty timing library is the numerical model STA uses for cell delay, output transition, and sequential constraints. Without a characterized .lib that matches the intended PVT and voltage, PrimeTime cannot compute a meaningful slack; the netlist alone is not enough. Treat library selection as part of the timing environment, not as a file you copy once and forget.

This chapter explains how NLDM lookup tables depend on input slew and output load, how CCS/ECSM current-source models improve accuracy at advanced nodes, and how timing arcs — including state-dependent arcs — tell the tool which pin-to-pin delays exist. Interviewers often jump from “what is a .lib?” to “what are the axes of an NLDM table?” in the same breath. A useful answer names the table axes, says delay is interpolated, and admits that a wrong-corner or missing library will make every downstream slack number look precise and still be wrong.

Key takeaways

  • Cell delay is looked up, not a single constant; slew and load move you around the table, and interpolation fills the gaps.
  • Setup and hold constraints live in the library as well as in SDC; both must be understood when reading a failing path.
  • NLDM is table-based; CCS/ECSM model current waveforms and generally correlate better when slew or load is extreme.
  • Missing, mismatched, or wrong-corner libraries are a leading cause of “the same netlist times differently.”

Interview angle: describe an NLDM lookup in one sentence (input transition, output capacitance, delay and slew out), then name one reason you might still need CCS at signoff.

Open the PDF reader for Liberty snippets, table sketches, and PrimeTime-oriented library examples that are easier to see than to describe in prose.

Previous: STA Concepts · Next: Interconnect Parasitics · Related questions: What is a Liberty library?, What is NLDM?, What is cell delay?

Sample interview answers

What does a Liberty timing library contain? NLDM or CCS/ECSM tables that give cell delay and output slew versus input slew and output load, plus pin capacitance and sequential constraints such as setup, hold, and recovery/removal.

Why does input slew matter as much as load? Delay tables are two-dimensional. A slow input transition lengthens cell delay and usually produces a slower output slew, which loads the next stage.

What happens if the linked library does not match the netlist cells? Timing arcs are missing or wrong, so paths are untimed or mis-timed with no obvious netlist error. Matching .lib, .db, and the cells actually instantiated is part of a trustworthy STA environment.

Continue: Interconnect parasitics · STA interview questions

💡 Key Technical Topics Covered

  • Non-Linear Delay Models (NLDM) Lookups
  • Composite Current Source (CCS) & ECSM Models
  • Combinational & Sequential Timing Arcs
  • State-Dependent Timing Arcs

🎯 VLSI Physical Design Interview Questions Addressed

  • What are the inputs to an NLDM table lookup?
  • What is the difference between NLDM and CCS timing models in PrimeTime?
  • Explain state-dependent timing arcs with an example XOR gate.